Timing considerations for the VE FVPs
The Rate Limit feature matches simulation time to wall-clock time.
The Fixed Virtual Platforms (FVPs) provide an environment that enables running software applications in a functionally-accurate simulation. However, because of the relative balance of fast simulation speed over timing accuracy, there are situations where the models might behave unexpectedly.
When code interacts with real world devices like timers and keyboards, data arrives in the modeled device in real world, or wall clock, time, but simulation time can run much faster than the wall clock. This means that a single key press might register as several repeated key presses, or a single mouse click incorrectly becomes a double click.
Enabling Rate Limit, either using the Rate Limit button in the CLCD display, or the
rate_limit-enable model instantiation parameter, forces the model to run
at wall-clock time. This avoids issues with two clocks running at significantly different
rates. For interactive applications, ARM recommends enabling Rate Limit.