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VE_SysRegs - ports

This section describes the ports.

Table 1. VE_SysRegs ports
Name Protocol Type Description
cb[0-1] VECBProtocol Master The Configuration Bus (CB) controls the power and reset sequence.
clk_24Mhz ClockSignal Slave Reference clock for internal counter register.
clk_100Hz ClockSignal Slave Reference clock for internal counter register.
clock_CLCD ClockRate Control Master The clock for the LCD controller.
lcd LCD Master Multimedia bus interface output to the LCD.
leds ValueState Master Displays state of the SYS_LED register using the eight colored LEDs on the status bar.
mmb[0-2] LCD Slave Multimedia bus interface input.
mmc_card_present StateSignal Slave Indicates the presence of a MultiMedia Card (MMC) image.
pvbus PVBus Slave Slave port for connection to PV bus master/decoder.
system_reset Signal Master Signal to the platform a complete system reset. Writes to the System Configuration registers can trigger the reset signal.
user_switches ValueState Master Provides state for the eight User DIP switches on the left side of the CLCD status bar, equivalent to switch S6 on VE hardware.

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