Base - differences between the AEMv8-A FVP and core FVPs
This section describes implementation features of the core models that the AEMv8-A model does not implement, or implements with significant differences.
- The default value of cache_state_modelled is 0.
- Components cluster0 and cluster1 are implementation cores, not AEMs. All parameters in these components are the parameters of the core implementation, not the parameters of the AEM. The values of bp.proc_id0 and bp.proc_id1 have fixed values consistent with the cores and are not configurable.
- The core defines the memory map of register banks within the GIC region, and the map is therefore not configurable. The parameter bp.variant communicates the nature of the memory map to target software. The parameter has a fixed value consistent with the memory map of the core, and is not configurable. Because the core implementations contain a specific version of the GIC, the parameter gicv3.gicv2-only is not available. The following registers in the GIC distributor are given fixed values to match the implementation, and are not configurable: gic_distributor.reg-base, gic_distributor.reg-base-per-distributor, gic_distributor.GICD-alias, gic_distributor.ITS0-base.
- The GICv2 CPU IDs are contiguous in implementation platform models, because the number of cores in each cluster is fixed. They can be noncontiguous in the AEMv8-A Base Platform FVP because there is space for four cores in the cluster. You can configure fewer than four cores.