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GICv3Distributor - parameters

This section describes the parameters. The processor has separate gic parameters, which are both gicv3 and gicv2.


Table 1. GICv3Distributor parameters
Name Type Allowed values Default value Description
a3_affinity_supported bool true, false false If true, support affinity level 3 values that are nonzero.
ARE_fixed_to_one bool true, false false If true, the model does not support GICv2 compatibility and GICD_CTLR.ARE_* is always one.
ARE_set_once bool true, false false If true, you can set GICD_CTLR.ARE_* but you can only reset them through reset.
collection_count int 0-65536 1024 Number of collections that each Interrupt Translation Services (ITS) component supports.
cpu_affinities string - "" Processing element affinity.
delay_ITS_accesses bool true, false true If true, delay accesses from the ITS until the model reads GICR_SYNCR (that is, until the architecture specification requires completion).
delay_redistributor_accesses bool true, false true If true, delay memory accesses from the redistributor until the model reads GICR_SYNCR.
DPG_bits_implemented bool true, false true If true, enable implementation of interrupt group participation bits or DPG bits in GICR_CTLR.
DS_fixed_to_zero bool true, false false If true, enable support of single security state.
enable_protocol_checking bool true, false false If true, enable protocol checking at the core interface.
enabled bool true, false true If true, enable this GICv3 component.
fixed_routed_spis string - "" Value of IROUTER[n] register in the form ' n=a.b.c.d, n=*'. The RM bit of IROUTER is 0 for n = a.b.c.d, else 1 for n = *. 32 <= n <= 1019.
gicd_alias uint64_t - 2C001000 Additional 4KB page in memory for the alias of GICD registers.
gicd_pidr uint64_t - 0

The value for the GICD_PIDR registers, if nonzero. Note: changing this value overrides fixed fields, such as device type.

gicr_pidr uint64_t - 0

The value for the GICR_PIDR registers, if nonzero. Note: changing this value overrides fixed fields, such as device type.

gicr_propbaser_read_only bool true, false false If true, the GICR_PROPBASER register is read-only.
gicr_propbaser_reset uint64_t - 0 Value of GICR_PROPBASER on reset.
gicv2_only bool true, false false If true, if using the GICv3 model, pretend to be a GICv2 system.
gits_basern_entry_bytes unsigned 1-256 8 Number of bytes for each entry for the GITS_BASERn register. 0 <= n <= 7.
gits_basern_type unsigned 0 - 4 0

Type field for the GITS_BASERn register. 0 <= n <= 7. 0 , unimplemented. 1 , devices. 2 , virtual processors. 3 , physical processors. 4 , collections.

gits_pidr uint64_t - 0

The value for the GITS_PIDR registers, if nonzero. Note: changing this value overrides fixed fields, such as device type.

has_two_security_states bool true, false true If true, has two security states.
icfgr_ppi_mask int 0 - FFFFFFFF AAAAAAAA Mask for writes to ICFGR registers that configure PPIs.
icfgr_ppi_reset int 0 - FFFFFFFF 0 Reset value for ICFGR registers that configure PPIs.
icfgr_ppi_rsvd_bits int 0 - FFFFFFFF 0 If ARE bit = 0, the value of reserved bits, that is, bits 0,2,4..30 of ICFGRn for n > 0.
icfgr_sgi_mask int 0 - FFFFFFFF 0 Mask for writes to ICFGR registers that configure SGIs.
icfgr_sgi_reset int 0 - FFFFFFFF AAAAAAAA Reset value for ICFGR registers that configure SGIs.
icfgr_spi_mask int 0 - FFFFFFFF AAAAAAAA Mask for writes to ICFGR registers that configure SPIs.
icfgr_spi_reset int 0 - FFFFFFFF 0 Reset value for ICFGR registers that configure SPIs.
ignore_generate_sgi_when_no_are bool true, false false If true, ignore GenerateSGI packets from the core interface if both ARE_S and ARE_NS are 0.
igroup_ppi_mask int 0 - FFFF FFFF Mask for writes to PPI bits in IGROUP registers.
igroup_ppi_reset int 0 - FFFF 0 Reset value for SGI bits in IGROUP registers.
igroup_sgi_mask int 0 - FFFF FFFF Mask for writes to SGI bits in IGROUP registers.
igroup_sgi_reset int 0 - FFFF 0 Reset value for SGI bits in IGROUP registers.
IIDR uint32_t 0 - FFFFFFFF 0 GICD_IIDR and GICR_IIDR value.
irouter_default_mask string - "" Default Mask value for the IROUTER[32..1019] register in the form a.b.c.d.
irouter_default_reset string - "" Default Reset value of the IROUTER[32..1019] register in the form a.b.c.d or *.
irouter_reset_values string - ""

Reset value of the IROUTER[n] register in the form n=a.b.c.d or n=*. 32 <= n <= 1019.

irouter_mask_values string - ""

Mask value of the IROUTER[n] register in the form n=a.b.c.d. 32 <= n <= 1019.

itargets_razwi bool true, false false If true, the GICD_ITARGETS registers are RAZ/WI.1
its_count int 0 - 4 1 Number of Interrupt Translation Services (ITS) components.
its_device_bits int 1-32 16 Number of bits that ITS device IDs support.
its_entry_size int 1 - 400 , 1-1024 8 , 8 Number of bytes to store each entry in the ITT tables.
ITS_hardware_collection_count int 0 - FF , 0-255 0 , 0 Number of hardware collections that the ITS holds exclusively.
its_id_bits int 14-24 16 Number of interrupt ID bits that ITS supports.
ITS-legacy-iidr-typer-offset bool true, false false If true, put the GITS_IIDR and GITS_TYPER registers at their older offset of 8 and 4 , respectively.
ITS_MOVALL_update_collections bool true, false false If true, the MOVALL command updates the collection entries.
ITS-supported-collection-count   0 - 400 400 Number of collections that each ITS component supports.
ITS_threaded_command_queue bool true, false true If true, enable the execution of ITS commands in a separate cosimulation thread.
ITS_TRANSLATE64R bool true, false false If true, add an implementation specific register at 10008 supporting 64-bit TRANSLATER (dev[63:32], interrupt[31:0]).
ITS_use_physical_target_addresses bool true, false true If true, use physical hardware addresses for targets in ITS commands. Must be true for distributed implementations.
itsn_base uint64_t 0 - ffffffffFFFFFFFF 0 Register base address for ITSn. This is automatic if 0. 0 <= n <= 3.
has-two-security-states bool true, false true If true, support two security states. If false, the GICD_CTLR.DS, DisableSecurity bit has a fixed value of 1.
local_SEIs bool true, false false If true, support locally generated SEIs to report internal issues.
local_VSEIs bool true, false false If true, support locally generated VSEIs to report internal issues.
lockable_spi_count int 0-31 0 Number of SPIs that the model locks down on assertion of the CFGSDISABLE signal. This only applies for GICv2.
LPI_cache_type int 0 - 1 1 Cache type for LPIs. 0 , no caching. 1 , extensive caching.
LPI_cache_check_data bool true, false false If true, enable cached LPI data against memory checking when available for cache type.
monolithic bool true, false false If true, the distributor is monolithic rather than distributed (modifies register behavior).
non_ARE_core_count int 1-8 8 Maximum number of non-ARE cores. The normal use is passing the cluster-level NUM_CORES parameter to the top-level redistributor.
pa_size int 32-48 48 Number of valid bits in physical address.
physical_id_bits int 16-24 16 Number of bits that represent physical interrupt ID.
ppi_implemented_mask int 0 - FFFF FFFF

Mask of PPIs that the model implements. One bit for each PPI bit 0 == PPI 16, first PPI. This affects other masks.

priority_bits_implemented uint32_t 4-8 8 Number of priority bits that the model implements.
processor_numbers string - "" Specifies processor numbers, as appear in GICR_TYPER, in the form 0.0.0.0 = 0,0.0.0.1 = 1. If this is not set, processor numbers start at 0.
redistributor_threaded_command_queue bool true, false true If true, enable the execution of redistributor delayed transactions in a cosimulation thread.
reg_base uint64_t - 2C010000 Base for decoding GICv3 registers.
reg_base_per_redistributor string - ""

Base address for each redistributor in the form '0.0.0.0 = 2C010000 , 0.0.0.1 = 2C020000 '.2

spi_count int 0 - 3DC , 0-988 E0 , 224 Number of SPIs that the model implements.
statusr_implemented bool true, false true If true, implement the GICR_STATUSR register.
supports_shareability bool true, false true If true, support shareability attributes on outgoing memory bus, that is, model an ACElite port not an AXI4 port.
trace_speculative_lpi_property_updates bool true, false false If true, perform LPI property updates on speculative accesses. Useful for debugging LPI.
virtual_id_bits int 16-24 16 Number of bits that represent virtual interrupt ID.
virtual_lpi_support bool true, false false If true, support GICv4 virtual LPIs and direct injection of virtual LPIs.

1 Legacy routing, GICv2-style, fixes interrupts to target the first processor in the system.
2 Specify all redistributors. This overrides the reg_base parameter for uses except that of the top-level redistributor.
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