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GICv3Distributor - ports

This section describes the ports.

Table 1. GICv3Distributor ports
Name Protocol Type Description
cfgsdisable Signal Slave Disable some SPI signals.
po_reset Signal Slave Power-on reset.
ppi_in_n[16] Signal Slave Private peripheral interrupts. 0 <= n <= 255.
pvbus_filtermiss_m PVBus Master Passthrough for undecoded accesses, when connected.
pvbus_m PVBus Master Memory bus out.1
pvbus_s PVBus Slave Memory bus in. The component accepts memory-mapped register accesses through this interface.
redistributor_m[256] GICv3Comms Master Input from and output to core interface.
reset Signal Slave Reset.
spi_in[988] Signal Slave Shared peripheral interrupts.
wake_request[256] Signal Master Power management outputs.

1 If you do not connect pvbus_filtermiss_m then it is the passthrough for undecoded accesses, plus it allows redistributors to access main memory. If you do connect pvbus_filtermiss_m, then only redistributor accesses to main memory appear on this port.
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