Base - VE compatibility - system global counter
The Generic Timer registers of the cores do not operate by default.
The model provides a memory-mapped interface to the system global counter, and enables the free-running timer from reset. However, the architectural requirement is that such a counter is not enabled at reset. As a result, the Generic Timer registers of the cores do not operate unless either:
- Software enables the counter peripheral by writing the FCREQ and EN bits in
. ARM recommends this approach.
-C bp.refcounter.non_arch_start_at_default=1parameter is set. This approach provides compatibility with older software.