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ClockDivider component

This section describes the ClockDivider component.

ClockDivider component - about

This component uses a configurable ratio to convert the ClockSignal rate at its input to a new ClockSignal rate at its output.

Changes to the input rate or ratio take effect immediately and clocking components dependent on the output rate continue counting at the new rate.

For examples of the use of ClockDividers, see the VEMotherBoard.lisa component in the %PVLIB_HOME%\examples\FVP_VE\LISA directory of your Fast Models distribution. On Linux, use the $PVLIB_HOME/examples/FVP_VE/LISA directory instead.

This is a C++ component.

ClockDivider - ports

This section describes the ports.

Table 4-20 ClockDivider ports

Name Protocol Type Description
clk_in ClockSignal Slave Source clock rate
clk_out ClockSignal Master Output clock rate
rate ClockRateControl Slave Permits you to dynamically change the clock divider ratio.

Related reference

ClockDivider - parameters

This section describes the parameters.


You can set these parameters from LISA but not SystemC.

Table 4-21 ClockDivider parameters

Name Type Allowed values Default value Description
mul uint_32 - 1 Clock rate multiplier
div uint_32 - 1 Clock rate divider

ClockDivider - verification and testing

This component was tested as part of the VE example system by running VE test suites and by booting operating systems.

ClockDivider - performance

This component does not normally incur a runtime performance cost. However, reprogramming the clock rate causes all related clocks and timers to be recalculated.