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MasterClock component

This section describes the MasterClock component.

MasterClock component - about

This component provides a single ClockSignal output that can be used to drive the ClockSignal input of ClockDividers, ClockTimers and other clocking components.

The rate of the MasterClock is not defined because all clocking is relative, but can be considered to be 1Hz.

A system might contain more than one MasterClock, all of which generate the same ClockSignal rate.

This is a C++ component.

MasterClock - ports

This section describes the ports.

Table 4-24 MasterClock ports

Name Protocol Type Description
clk_out ClockSignal Master Master clock rate

For more information, see the hardware documentation.

MasterClock - verification and testing

This component passes tests as part of the VE example system by using VE test suites and by booting operating systems.