GIC_400 component
This section describes the GIC_400 component.
GIC_400 - about
This LISA+ component is a model of r0p1 of the GIC-400 Generic Interrupt Controller (GIC), and includes a Virtualized Generic Interrupt Controller (VGIC).
It is a wrapper that permits easier configuration of the v7_VGIC component that supports parameterized configuration.
The GIC-400 has several memory-mapped interfaces at the same address. The
processor that is communicating with the GIC-400 banks them. The GIC-400 must be able to
distinguish from which processor a transaction originates. In the hardware, the AUSER
fields on AXI supply this information to the GIC-400. In Fast Models, there is no exact
equivalent to this field. However, each transaction has a master_id
that the model can use to identify the originating
processor.
ARM® clusters assign the master_id
as follows:
- Bits[31:16]: SBZ (which the GIC-400 ignores).
- Bits[5:2]: CLUSTERID.
- Bits[1:0]: cpu_id within cluster.
CLUSTERID is the 4-bit field that either a parameter on the processor
sets or a value on the clusterid
port drives. CPUID is
the core number within the cluster. CLUSTERID appears in the CP15 register space as part
of the MPIDR register.
The ARM architecture suggests that each cluster in the system is given a
different CLUSTERID. This distinction is essential for the VGIC to identify the cluster.
The parameters in the GIC-400 component permit it to construct the map of master_id
to interface number.
Processor interfaces that the GIC-400 supports have these parameters:
interfaceN.cluster_id
.interfaceN.core_id
.interfaceN.inout_port_number_to_use
.
N is the interface number (0-7). The cluster_id
and core_id
tell the GIC-400
to map that cluster or core combination to interface N.
In using inout_port_number_to_use
, the
GIC-400 has some input and output ports that pair with a particular processor interface.
For example:
- The
irqcpu[]
pin wires to theirq
port of the corresponding processor. - The
cntpnsirq
pin from the processor wires to acntpnsirq[]
pin on GIC-400 to transport a Private Peripheral Interrupt (PPI) from the processor to the GIC-400.
The interfaceN.inout_port_number_to_use
parameter supports clusters that can have variable numbers of cores. It tells the
GIC-400 that to send to or receive a signal from the processor that is attached to
interface N, it must use these pins:
irqout[interfaceN.inout_port_number_to_use]
.fiqout[interfaceN.inout_port_number_to_use]
.virqout[interfaceN.inout_port_number_to_use]
.vfiqout[interfaceN.inout_port_number_to_use]
.legacyirq[interfaceN.inout_port_number_to_use]
.cntpnsirq[interfaceN.inout_port_number_to_use]
.cntpsirq[interfaceN.inout_port_number_to_use]
.legacyfiq[interfaceN.inout_port_number_to_use]
.cntvirq[interfaceN.inout_port_number_to_use]
.cnthpirq[interfaceN.inout_port_number_to_use]
.- ...
legacyirq
and legacyfiq
are not signals from the processor but are signals into the
GIC-400 from the legacy interrupt system. They are wired to PPIs. If the control
registers of the GIC-400 are set up in particular ways, they can also bypass the
GIC-400. See the ARM Generic Interrupt Controller Architecture
version 2.0 Architecture Specification for more information.
The fabric between the clusters and the GIC might remap the master_id
of a transaction. If so, then the GIC might lose
the ability to identify the originating processor. The fabrics that ARM ships in Fast
Models perform no such transformation.
The comparison that the GIC-400 performs on the master_id
is only on the bottom 6 bits of the master_id
. It ignores the rest. If you are writing your own fabric and do
not properly propagate the master_id
or transform it,
the GIC-400 might not be able to identify the processor. The source code for the GIC_400
component can be examined to see how it might be adapted for it to understand different
master_id
schemes.
The GIC-400 model has these limitations:
- Reads and writes to GICD_ISACTIVERn/GICD_ICACTIVERn/GICD_ISPENDRn/GICD_ICPENDRn might not work as expected unless there is a configured target in GICD_ICFGRm.
- Some of the interaction of GICD_CTLR.EnableGrpX and level sensitive interrupts might not work entirely correctly.
- It does not model the signals nIRQOUT/nFIQOUT.
- It models interrupts with positive logic, rather than the negative logic that the hardware uses. Hence, the signal pins omit the "n" prefix in their names.
GIC_400 - ports
This section describes the ports.
Table 4-59 GIC_400 ports
Name | Protocol | Type | Description |
---|---|---|---|
cfgsdisable |
Signal | Slave | Disable write access to some GIC registers. |
cnthpirq |
Signal | Slave | Hypervisor physical timer event. |
cntpnsirq |
Signal | Slave | Non-secure physical timer event. |
cntpsirq |
Signal | Slave | Secure physical timer event. |
cntvirq |
Signal | Slave | Virtual timer event. |
fiqcpu |
Signal | Master | FIQ signal to the corresponding processor. |
fiqout |
Signal | Master | FIQOUT signal to the corresponding processor. |
irqcpu |
Signal | Master | IRQ signal to the corresponding processor. |
irqout |
Signal | Master | IRQOUT signal to the corresponding processor. |
irqs |
Signal | Slave | Interrupt request input lines for the GIC. |
legacyfiq |
Signal | Slave | Signal into the GIC-400 from the legacy interrupt system. |
legacyirq |
Signal | Slave | Signal into the GIC-400 from the legacy interrupt system. |
pvbus_s |
PVBus | Slave | Handles incoming transactions from PVBus masters. |
reset_signal |
Signal | Slave | Reset signal input. |
vfiqcpu |
Signal | Master | Virtual FIQ signal to the processor. |
virqcpu |
Signal | Master | Virtual IRQ signal to the processor. |
GIC_400 - parameters
This section describes the parameters.
Table 4-60 GIC_400 parameters
Name | Type | Allowed values | Default value | Description |
---|---|---|---|---|
NUM_CPUS |
Integer | 1-8 | 1 | Number of interfaces to support. |
NUM_SPIS |
Integer | 0-480 | 224 | Number of shared peripheral interrupt pins. |
interface0.cluster_id |
Integer | 0-15 | 0 | Cluster ID of the interface you want to appear as interface0 in
the VGIC. |
interface0.core_id |
Integer | 0-15 | 0 | Core ID of interface0 in the cluster. |
interface0.inout_port_number_to_use |
Integer | 0-7 | 0 | ppiN port used for this interface. |
interface1.cluster_id |
Integer | 0-15 | 0 | Cluster ID of the interface you want to appear as interface1 in
the VGIC. |
interface1.core_id |
Integer | 0-15 | 0 | The Core ID of interface1 in the cluster. |
interface1.inout_port_number_to_use |
Integer | 0-7 | 1 | ppiN port used for this interface. |
interface2.cluster_id |
Integer | 0-15 | 0 | Cluster ID of the interface you want to appear as interface2 in
the VGIC. |
interface2.core_id |
Integer | 0-15 | 0 | Core ID of interface2 in the cluster. |
interface2.inout_port_number_to_use |
Integer | 0-7 | 2 | ppiN port used for this interface. |
interface3.cluster_id |
Integer | 0-15 | 0 | Cluster ID of the interface you want to appear as interface3 in
the VGIC. |
interface3.core_id |
Integer | 0-15 | 0 | Core ID of interface3 in the cluster. |
interface3.inout_port_number_to_use |
Integer | 0-7 | 3 | ppiN port used for this interface. |
interface4.cluster_id |
Integer | 0-15 | 0 | Cluster ID of the interface you want to appear as interface4 in
the VGIC. |
interface4.core_id |
Integer | 0-15 | 0 | Core ID of interface4 in the cluster. |
interface4.inout_port_number_to_use |
Integer | 0-7 | 4 | ppiN port used for this interface. |
interface5.cluster_id |
Integer | 0-15 | 0 | Cluster ID of the interface you want to appear as interface5 in
the VGIC. |
interface5.core_id |
Integer | 0-15 | 0 | Core ID of interface5 in the cluster. |
interface5.inout_port_number_to_use |
Integer | 0-7 | 5 | ppiN port used for this interface. |
interface6.cluster_id |
Integer | 0-15 | 0 | Cluster ID of the interface you want to appear as interface6 in
the VGIC. |
interface6.core_id |
Integer | 0-15 | 0 | Core ID of interface6 in the cluster. |
interface6.inout_port_number_to_use |
Integer | 0-7 | 6 | ppiN port used for this interface. |
interface7.cluster_id |
Integer | 0-15 | 0 | Cluster ID of the interface you want to appear as interface7 in
the VGIC. |
interface7.core_id |
Integer | 0-15 | 0 | Core ID of interface7 in the cluster. |
interface7.inout_port_number_to_use |
Integer | 0-7 | 7 | ppiN port used for this interface. |
GIC_400 - registers
This component provides the registers that the Technical Reference Manual (TRM) specifies.
GIC_400 - verification and testing
This component passes tests as part of a system with network functionalities.