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GICv3IRI_Filter component

This section describes the GICv3IRI_Filter component.

GICv3IRI_Filter - about

The GICv3IRI_Filter component is a configurable architectural model of the GICv3/GICv4 Interrupt Routing Infrastructure, validation-only version.

The GICv3IRI_Filter has similar behavior to the GICv3IRI, except for the slave interface. Any transaction accessing a 4KB page that is not used by the GIC, as configurable through the parameters, is forwarded to the pvbus_filtermiss_m port, which is only present in this variant.

GICv3IRI_Filter - ports

This table describes the ports.

Table 4-67 GICv3IRI_Filter ports

Name Protocol Type Description
cfgsdisable Signal Slave Disable some SPI signals.
po_reset Signal Slave Power-on reset.
ppi_in_n[16] Signal Slave Private peripheral interrupts. 0 <= n <= 255.
pvbus_filtermiss_m PVBus Master Passthrough for accesses to pages not used by the GIC IRI.
pvbus_m PVBus Master Memory bus for transactions generated by the GIC.
pvbus_s PVBus Slave Memory bus in.
redistributor_m[256] GICv3Comms Master Input from and output to the core interface.
reset Signal Slave Reset.
spi_in[988] Signal Slave Shared peripheral interrupts.
wake_request[256] Signal Master Power management outputs.

GICv3IRI_Filter - parameters

This table describes the GICv3IRI_Filter parameters.

Table 4-68 GICv3IRI_Filter parameters

Name Type Allowed values Default value Description
A3-affinity-supported bool true, false false If true, support affinity level 3 values that are non-zero.
ARE-fixed-to-one bool true, false false If true, the model does not support GICv2 compatibility and GICD_CTLR.ARE_* is always one.
common-lpi-configuration int 0-3 0 Describes which Redistributors share, and must be configured with, the same LPI Configuration table, as described in GICR_TYPER. 0: All, 1: A.x.x.x, 2: A.B.x.x, 3: A.B.C.x.
CPU-affinities string - "" Processing element affinity.
delay-ITS-accesses bool true, false true If true, delay accesses from the ITS until the model reads GICR_SYNCR (that is, until the architecture specification requires completion).
delay-redistributor-accesses bool true, false true If true, delay memory accesses from the Redistributor until the model reads GICR_SYNCR.
direct-lpi-support bool true, false false Enable support for LPI operations through GICR registers.
DPG-ARE-only bool true, false true Limit the application of DPG bits to interrupt groups for which ARE=1.
DPG-bits-implemented bool true, false true If true, enable implementation of interrupt group participation bits or DPG bits in GICR_CTLR.
DS-fixed-to-zero bool true, false false If true, enable support of a single security state.
enable_protocol_checking bool true, false false If true, enable protocol checking at the core interface.
enabled bool true, false true If true, enable this GICv3 component.
fixed-routed-spis string - "" Value of IROUTER[n] register in the form 'n=a.b.c.d, n=*'. The RM bit of IROUTER is 0 for n = a.b.c.d, else 1 for n = *. 32 <= n <= 1019.
GICD-alias uint64_t - 0 In GICv2 mode, the base address for a 4KB page alias of the first 4KB of the Distributor page. In GICv3 mode, the base address of a 64KB page containing message based SPI signalling register aliases (0: disabled).
GICD_ITARGETSR-RAZWI bool true, false false If true, the GICD_ITARGETS registers are RAZ/WI.a
GICD_PIDR uint64_t - 0x0

The value for the GICD_PIDR registers, if non-zero.

Note

Changing this value overrides fixed fields, such as device type.
GICR_PIDR uint64_t - 0x0

The value for the GICR_PIDR registers, if non-zero.

Note

Changing this value overrides fixed fields, such as device type.
GICR_PROPBASER-read-only bool true, false false If true, the GICR_PROPBASER register is read-only.
GICR_PROPBASER-reset-value uint64_t - 0x0 Value of GICR_PROPBASER on reset.
gicv2-only bool true, false false If true, when using the GICv3 model, pretend to be a GICv2 system.
GITS_BASERn-entry-bytes unsigned 1-256 8 Number of bytes for each entry in the GITS_BASERn register. 0 <= n <= 7.
GITS_BASERn-type unsigned 0x0-0x4 0x0

Type field for the GITS_BASERn register. 0 <= n <= 7. 0x0 = Unimplemented, 0x1 = Devices, 0x2 = Virtual Processors, 0x4 = Collections. Other values are reserved.

GITS_PIDR uint64_t - 0x0

The value for the GITS_PIDR registers, if non-zero.

Note

Changing this value overrides fixed fields, such as device type.
has-two-security-states bool true, false true If true, support two security states. If false, the GICD_CTLR.DS Disable Security bit has a fixed value of 1.
ICFGR-PPI-mask int 0x0-0xFFFFFFFF 0xAAAAAAAA Mask for writes to ICFGR registers that configure PPIs.
ICFGR-PPI-reset int 0x0-0xFFFFFFFF 0x0 Reset value for ICFGR registers that configure PPIs.
ICFGR-rsvd-bit int 0x0-0xFFFFFFFF 0x0 If ARE bit = 0, the value of reserved bits, that is, bits 0, 2, 4…30 of ICFGRn for n > 0.
ICFGR-SGI-mask int 0x0-0xFFFFFFFF 0x0 Mask for writes to ICFGR registers that configure SGIs.
ICFGR-SGI-reset int 0x0-0xFFFFFFFF 0xAAAAAAAA Reset value for ICFGR registers that configure SGIs.
ICFGR-SPI-mask int 0x0-0xFFFFFFFF 0xAAAAAAAA Mask for writes to ICFGR registers that configure SPIs.
ICFGR-SPI-reset int 0x0-0xFFFFFFFF 0x0 Reset value for ICFGR registers that configure SPIs.
ignore-generate-sgi-when-no-are bool true, false false If true, ignore Generate SGI packets from the core interface if both ARE_S and ARE_NS are 0.
IGROUP-PPI-mask int 0x0-0xFFFF 0xFFFF Mask for writes to PPI bits in IGROUP registers.
IGROUP-PPI-reset int 0x0-0xFFFF 0x0 Reset value for SGI bits in IGROUP registers.
IGROUP-SGI-mask int 0x0-0xFFFF 0xFFFF Mask for writes to SGI bits in IGROUP registers.
IGROUP-SGI-reset int 0x0-0xFFFF 0x0 Reset value for SGI bits in IGROUP registers.
IIDR uint32_t 0x0-0xFFFFFFFF 0x0 GICD_IIDR and GICR_IIDR value.
IRI-ID-bits int 16-24 16 Number of bits used to represent interrupt IDs in the Distributor and Redistributors.
IROUTER-IRM-RAZ-WI bool true, false false GICD_IROUTERn.Interrupt_Routing_Mode is RAZ/WI.
irouter-default-mask string - "" Default mask value for the IROUTER[32..1019] register in the form a.b.c.d.
irouter-default-reset string - "" Default reset value of the IROUTER[32..1019] register in the form a.b.c.d or *.
irouter-mask-values string - ""

Mask value of the IROUTER[n] register in the form n=a.b.c.d. 32 <= n <= 1019.

irouter-reset-values string - ""

Reset value of the IROUTER[n] register in the form n=a.b.c.d or n=*. 32 <= n <= 1019.

ITS-BASER-force-page-alignement bool true, false true Force alignment of the address written to a GITS_BASER register to the page size configured.
ITS-collection-ID-bits int 0-16 0 Number of collection ID bits supported by ITS. This is an optional parameter, 0 = 16-bit support and GITS_TYPER.CIL=0.
ITS-count int 0x0-0x4 0 Number of Interrupt Translation Service (ITS) components.
ITS-cumulative-collection-tables bool true, false false When true, the supported number of collections is the sum of GITS_TYPER.HCC and the number of collections supported in memory, otherwise, the number supported in memory only. Irrelevant when HCC=0.
ITS-device-bits int 1-32 16 Number of bits that ITS device IDs support.
ITS-entry-size int 1-1024 8 Number of bytes to store each entry in the ITT tables.
ITS-hardware-collection-count int 0-255 0 Number of hardware collections that the ITS holds exclusively.
ITS-ID-bits int 14-24 16 Number of incoming interrupt ID bits that ITS supports.
ITS-MOVALL-update-collections bool true, false false If true, the MOVALL command updates the collection entries.
ITS-threaded-command-queue bool true, false true If true, enable the execution of ITS commands in a separate cosimulation thread.
ITS-TRANSLATE64R bool true, false false If true, add an implementation-specific register at 0x10008 supporting 64-bit TRANSLATER (dev[63:32], interrupt[31:0]).
ITS-use-physical-target-addresses bool true, false true If true, use physical hardware addresses for targets in ITS commands. Must be true for distributed implementations.
ITSn-base uint64_t 0x0-0xffffffffFFFFFFFF 0x0 Register base address for ITSn. This is automatic if 0. 0 <= n <= 3.
legacy-sgi-enable-rao bool true, false false Enables for SGIs associated with an ARE=0 regime are RAO/WI.
local-SEIs bool true, false false If true, support locally generated SEIs to report internal issues.
local-VSEIs bool true, false false If true, support locally generated VSEIs to report internal issues.
lockable-SPI-count int 0-31 0 Number of SPIs that the model locks down on assertion of the CFGSDISABLE signal. This only applies to GICv2.
LPI-cache-type int 0x0-0x1 0x1 Cache type for LPIs. 0x0, no caching. 0x1, extensive caching.
LPI-cache-check-data bool true, false false If true, enable cached LPI data against memory checking when available for cache type.
monolithic bool true, false false If true, the Distributor is monolithic rather than distributed (modifies register behavior).
non-ARE-core-count int 1-8 8 Maximum number of non-ARE cores. The normal use is passing the cluster-level NUM_CORES parameter to the top-level Redistributor.
PA_SIZE int 32-48 48 Number of valid bits in the physical address.
physical-ID-bits int 16-24 16 Number of physical ID bits implemented. This is deprecated. Use iri_id_bits instead.
PPI-implemented-mask int 0x0-0xFFFF 0xFFFF

Mask of the PPIs that the model implements. One bit for each PPI bit. 0 == PPI 16, first PPI. This affects other masks.

priority-bits uint32_t 4-8 8 Number of priority bits that the model implements.
processor-numbers string - "" Specifies processor numbers, as they appear in GICR_TYPER, in the form 0.0.0.0 = 0, 0.0.0.1 = 1. If this is not set, processor numbers start at 0.
redistributor-threaded-sync bool true, false true If true, enable the execution of Redistributor delayed transactions in a cosimulation thread.
reg-base uint64_t - 0x2C010000 Base for decoding GICv3 registers.
reg-base-per-redistributor string - ""

Base address for each Redistributor in the form 0.0.0.0 = 0x2C010000, 0.0.0.1 = 0x2C020000.b

SPI-count int 0-988 224 Number of SPIs that the model implements.
SPI-message-based-support bool true, false true In GICv3/v4, the Distributor supports message-based signalling of SPI.
SPI-unimplemented string - "" A comma-separated list of unimplemented SPI ranges, for sparse SPI definition. For example, 35, 39-42, 73.
STATUSR-implemented bool true, false true If true, implement the GICR_STATUSR register.
supports-shareability bool true, false true If true, support shareability attributes on outgoing memory bus, that is, model an ACElite port not an AXI4 port.
trace-speculative-lpi-property-update bool true, false false If true, perform LPI property updates on speculative accesses. Useful for debugging LPI.
virtual-ID-bits int 16-24 16 Number of virtual bits implemented. This is deprecated. Use iri_id_bits instead.
virtual-lpi-support bool true, false false If true, support GICv4 virtual LPIs and direct injection of virtual LPIs.
a Legacy routing, GICv2-style, fixes interrupts to target the first processor in the system.
b Specify all Redistributors. This overrides the reg_base parameter for uses except that of the top-level Redistributor.
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