This section describes the IntelStrataFlashJ3 component.
IntelStrataFlashJ3 - about
This component is an efficient implementation of a NOR Flash memory type device, an Intel StrataFlash Memory (J3).
In normal usage, the device acts as Read Only Memory (ROM) whose contents can be determined either by programming using the flashloader port or by using standard flash programming software run on the model, such as the ARM® Firmware Suite.
This component implementation is approximately that of the Intel part in the VE development board. The component is effectively organized as a bank of two 16-bit Intel Flash components forming a 32-bit component that can be read or programmed in parallel. The component supports all hardware behavior except for:
- Protection register.
- Enhanced configuration register.
- Unique device identifier.
- One time programmable cells.
- Suspend/resume, which is silently ignored.
- Status interrupt line.
All block operations are atomic. This means that the status register state machine status bit always reads 1, ready.
This is a LISA+ component.
IntelStrataFlashJ3 - ports
This section describes the ports.
Table 4-74 IntelStrataFlashJ3 component ports
||FlashLoaderPort||Slave||Permits a FlashLoader component to initialize the flash contents from a binary file|
||PVBusSlaveControl||Master||ARM test control|
||PVDevice||Slave||ARM test control|
||PVBus||Slave||Slave port for connection to PV bus master/decoder|
IntelStrataFlashJ3 - parameters
This section describes the parameters.
Table 4-75 IntelStrataFlashJ3 component parameters
|Name||Type||Allowed values||Default value||Description|
||Per block locking.|
||â‰¥256KB, â‰¤4GB||256KB||Component size in bytes, in multiples of 256KB (18 bits).|
||Generate abort on write. Use when modeling ROM with flash memory.|
||Writes to flash are overwrite not AND. Use when debugging drivers.|
IntelStrataFlashJ3 - registers
In normal operation, the component has no user visible registers, but you can read from it as if it is memory.
Programming it or changing the configuration requires a sequence of special write
operations: see general flash programming documentation. Note that the model interprets all
writes as requests to the programming state machine, and that there are many state-machine
states that do not support subsequent reads and return
for them. Therefore, when simulating a ROM, use the
trapwrite=true option. The component supports Common Flash Interface
query operations, which allow drivers to determine the properties of the flash memory.
IntelStrataFlashJ3 - debug features
Read/write to this component using normal debugWrites.
diagnostics parameter to select the level of diagnostic
- Level 0
- Level 1
Report probable driver error operations:
- Unaligned operations that fault.
- Accesses that the state machine does not expect.
- Transitions of the state machine to unknown states.
- Writes to locked blocks and illegal lock commands.
- Level 2
Report unimplemented and so ignored operations, and log lock commands.
- Level 3
- Warn if a flash write attempts to set bits (the
write works if
- Level 4
- Log every read and write.
IntelStrataFlashJ3 - verification and testing
This component passes tests as part of the VE example system by using VE test suites and by booting operating systems.