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MMU_500 component

This section describes the MMU_500 component.

MMU_500 - about

This LISA+ component is a model of a basic MMU-500. Set the version with the version parameter.

You cannot arbitrarily configure how you derive StreamIDs and SSD_Indexes from the transaction attributes.

This component has two label modes: you select which one with the parameter use_label_mapping.

MMU_500 - ports

This section describes the ports.

Table 4-89 MMU_500 ports

Name Protocol Type Description
cfg_cttw_in Signal Slave Enables coherent page table walks.
cxt_irpt[128] Signal Master Context interrupt.
comb_irpt_ns Signal Master Non-secure combined interrupt.
comb_irpt_s Signal Master Secure combined interrupt.
glbl_flt_irpt_ns Signal Master Global Non-secure fault interrupt.
glbl_flt_irpt_s Signal Master Global Secure fault interrupt.
pvbus_control_s PVBus Slave Provides memory-mapped read write access to the control registers of the module.
pvbus_m[32] PVBus Master For all memory accesses. One for each Translation Buffer Unit (TBU).
pvbus_ptw_m PVBus Master If ptw_has_separate_port is true, use for page table walks.
pvbus_s[32] PVBus Slave For transactions from PVBus master/decoder. One for each TBU.
reset_in Signal Slave Reset signal.

MMU_500 - parameters

This section describes the parameters.

Table 4-90 MMU_500 parameters

Name Type Allowed values Default value Description
always_secure_ssd_indices string - "" Non-programmable Security State Determination (SSD) indexes that are always Secure, for example 0, 6, 35-64.
cfg_cttw bool true, false true Perform coherent page table walks.
dump_unpredictablity_in_user_flags bool true, false false Override the user flags to encode unpredictable information (validation only).
number_of_contexts unsigned 1-128 8 Number of context banks.
number_of_smrs unsigned 2-128 32 Number of stream match registers.
percent_tlbstatus_commits uint32_t 1-100 10 Percentage of times that a poll of TLBSTATUS will commit the TLBI commands.
programmable_non_secure_by_default_ssd_indices string - "" Programmable SSD indexes that are by default Non-secure, for example 0, 6, 35-84.
programmable_secure_by_default_ssd_indices string - "" Programmable SSD indexes that are by default Secure, for example 0, 6, 35-84.
ptw_has_separate_port bool true, false true Page table walks use pvbus_ptw_m.
pvbus_ptw_m_is_ace_lite bool true, false true pvbus_ptw_m port is ACE-Lite.
supports_nested_translations bool true, false true Supports nested translations (stage 1 + stage 2).
tlb_depth unsigned 0-2048 2048 TLB depth. 0 means 'infinite'.
use_ssd_determination_table bool true, false true Use the SSD determination table.a
version string - "" Version of the RTL that the model represents. Valid values are LACr1 and EAC. The default is empty, for which the simulation fails on startup.

MMU_500 - identify() parameters

The ARM implementation of the identify() function uses these parameters to map a label of a transaction to a StreamID and either an SSD_Index or a Security State Determination (SSD).

Note

The labelN_ parameters are only used if use_label_mapping is true.

Table 4-91 MMU_500 identify() parameters

Name Type Allowed values Default value Description
use_label_mapping bool true, false true This component has two label modes. You select which one with this parameter.b
labelN_read_ssd unsigned 0-65535 0 LabelN: read SSD or SSD_Index. 0 <= N <= 31.
labelN_read_stream_id unsigned 0-65535 0 LabelN: read StreamID. 0 <= N <= 31.
labelN_write_ssd unsigned 0-65535 0 LabelN: write SSD or SSD_Index. 0 <= N <= 31.
labelN_write_stream_id unsigned 0-65535 0 LabelN: write StreamID. 0 <= N <= 31.

MMU_500 - registers

This section describes the registers.

This component models all architectural registers as the Technical Reference Manual (TRM) specifies, except for performance registers. It does not model any of the performance registers.

Unlike the MMU-400, MMU-500 does have an SMMU_STLBGSTATUS register because it has stage 1 and stage 2 support.

The SMMU_NSACR is an alias of the Non-secure SMMU_ACR. This component models SMMU_ACR as RAZ/WI.

The *ACR registers have IMP DEF contents. This component models only the PAGESIZE bit of the SACR, as non-RAZ/WI. It models no other IMP DEF registers.

a If true, the bottom 16 bits of the MasterID encode the SSD_Index. They must be < 2^ssd_index_width. If false, they encode the SSD state directly (zero is Secure and nonzero is Non-secure).
b Use true if your upstream devices have labels in the top 16 bits of the transaction MasterID. Note that the model does not have a concept of AXI-ID, but a transaction can have a MasterID set on it. Label your upstream components 0…N so that the parameters of this component can map those integers to StreamID and SSD_Index. Use false if the StreamID is encoded in the top 16 bits of the MasterID and the bottom 16 bits encode either the SSD_Index or the SSD state directly, depending on use_ssd_determination_table. Typically in hardware, a device emits different AXI-IDs, depending on what it is doing. In the model, MasterIDs are usually not diverse and a device might only emit one MasterID.
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