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PL330_DMAC component

This section describes the PL330_DMAC component.

PL330_DMAC - about

This LISA+ component is a model of the ARM® PrimeCell Dynamic Memory Access Controller (PL330).

The model uses a single LISA component but with a C++ model for each of the channels included in the LISA file. Enabled channels are kept on an enabled_channels stack in priority order. When a channel state changes, rearbitration takes place to make the highest (topmost) channel active.

PL330_DMAC - transaction labels

Each transaction carries the identity of the requesting thread.

This controller has up to eight channel threads and a manager thread. Each has an ID. In the hardware, the ID is AxID[3:0], with 0x0 - (number of channels – 1) identifying channels and (number of channels) identifying the manager: for example, 0x0-0x7 and 0x8, respectively. The manager originates only instruction fetches, and the manager ID is also used for instruction fetches issued by the channels.

In the model, the identity of the requesting thread is encoded into each transaction using the low-order 16 bits of the Master ID field:

  • Channel data: 0-7.
  • Channel instruction fetch: 0xffff.
  • Manager instruction fetch: 0xffff.

If a downstream component needs to know the IDs of bus masters that use either the low-order 16 bits or the label, use the label. The LabellerForDMA330 component shifts the low-order 16 bits into the label, while providing a degree of control over the label encoding. The example below maintains separate IDs for each data channel while using the correct hardware ID to identify instruction fetch for a DMA-330 with 8 channels:

pl330_dma : PL330_DMAC( "p_max_channels" = 8 );
dma_labeller : LabellerForDMA330(
    "dma330_discriminate_data_channels" = true,
    "dma330_s_instruction_label" = 8,
    "dma330_ns_instruction_label" = 8 );
pl330_dma.pvbus_m => dma_labeller.pvbus_s;
dma_labeller.pvbus_m => output_bus.pvbus_s;

PL330_DMAC - ports

This section describes the ports.

Table 4-124 PL330_DMAC ports

Name Protocol Type Description
clk_in ClockSignal Slave Main processor clock input.
irq_abort_master_port Signal Master Undefined instruction or instruction error.
irq_master_port[32] Signal Master Sets when DMASEV.
pvbus_m PVBus Master Master port for all memory accesses.
pvbus_s PVBus Slave Slave port for all register accesses (secure).
pvbus_s_ns PVBus Slave Slave port for all register accesses (non-secure).
reset_in Signal Slave System reset signal.

PL330_DMAC - parameters

This section describes the parameters.

Table 4-125 PL330_DMAC parameters

Name Type Allowed values Default value Description
activate_delay uint32_t - 0 Request delay.
fifo_size uint32_t - 16 Channel FIFO size in bytes.
generate_clear bool true, false false Generate clear response.
max_transfer uint32_t - 256 Largest atomic transfer.
p_axi_bus_width_param uint32_t 32-128 32 AXI bus width.
p_buffer_depth uint32_t - 16 Buffer depth.
p_cache_lines uint32_t - 1 Number of cache lines.
p_cache_line_words uint32_t - 1 Number of words in a cache line.
p_controller_boots bool true, false true DMA boots from reset.
p_controller_nsecure bool true, false false Controller non-secure at reset.
p_irq_nsecure uint32_t - 0 Interrupts non-secure at reset.
p_lsq_read_size uint32_t   4 LSQ read buffer depth.
p_lsq_write_size uint32_t - 4 LSQ write buffer depth.
p_max_channels uint32_t ≤8 8 Virtual channels.
p_max_irqs uint32_t 0-32 32 Number of interrupts.
p_max_periph uint32_t - 32 Number of peripheral interfaces.
p_periph_nsecure bool true, false false Peripherals non-secure at reset.
p_perip_request_acceptance_n uint32_t - 2 Peripheral n request acceptance, where 0 <= n <=31.
p_read_issuing_capability uint32_t - 1 AXI read issuing capability.
p_reset_pc uint32_t Any valid address 0x60000000 DMA PC at reset.
p_write_issuing_capability uint32_t - 1 AXI write issuing capability.
revision string   "r0p0" Revision ID.

PL330_DMAC - registers

This section describes the registers.

Table 4-126 PL330_DMAC registers

Name Offset Access Description
DS 0x000 Read only DMA status register
DPC 0x004 Read only DMA program counter register
INTEN 0x020 Read/write Interrupt enable register
ES 0x024 Read only Event status register
INTSTATUS 0x028 Read only Interrupt status register
INTCLR 0x02c Write only Interrupt clear register
FSM 0x030 Read only Fault status DMA manager register
FSC 0x034 Read only Fault status DMA channel register
FTM 0x038 Read only Fault type DMA manager register
FTC0 0x040 Read only Fault type for DMA channel 0
FTC1 0x044 Read only Fault type for DMA channel 1
FTC2 0x048 Read only Fault type for DMA channel 2
FTC3 0x04c Read only Fault type for DMA channel 3
FTC4 0x050 Read only Fault type for DMA channel 4
FTC5 0x054 Read only Fault type for DMA channel 5
FTC6 0x058 Read only Fault type for DMA channel 6
FTC7 0x05c Read only Fault type for DMA channel 7
CS0 0x100 Read only Channel status for DMA channel 0
CS1 0x108 Read only Channel status for DMA channel 1
CS2 0x110 Read only Channel status for DMA channel 2
CS3 0x118 Read only Channel status for DMA channel 3
CS4 0x120 Read only Channel status for DMA channel 4
CS5 0x128 Read only Channel status for DMA channel 5
CS6 0x130 Read only Channel status for DMA channel 6
CS7 0x138 Read only Channel status for DMA channel 7
CPC0 0x104 Read only Channel PC for DMA channel 0
CPC1 0x10c Read only Channel PC for DMA channel 1
CPC2 0x114 Read only Channel PC for DMA channel 2
CPC3 0x11c Read only Channel PC for DMA channel 3
CPC4 0x124 Read only Channel PC for DMA channel 4
CPC5 0x12c Read only Channel PC for DMA channel 5
CPC6 0x134 Read only Channel PC for DMA channel 6
CPC7 0x13c Read only Channel PC for DMA channel 7
SA_0 0x400 Read only Source address for DMA channel 0
SA_1 0x420 Read only Source address for DMA channel 1
SA_2 0x440 Read only Source address for DMA channel 2
SA_3 0x460 Read only Source address for DMA channel 3
SA_4 0x480 Read only Source address for DMA channel 4
SA_5 0x4A0 Read only Source address for DMA channel 5
SA_6 0x4C0 Read only Source address for DMA channel 6
SA_7 0x4E0 Read only Source address for DMA channel 7
DA_0 0x404 Read only Destination address for DMA channel 0
DA_1 0x424 Read only Destination address for DMA channel 1
DA_2 0x444 Read only Destination address for DMA channel 2
DA_3 0x464 Read only Destination address for DMA channel 3
DA_4 0x484 Read only Destination address for DMA channel 4
DA_5 0x4A4 Read only Destination address for DMA channel 5
DA_6 0x4C4 Read only Destination address for DMA channel 6
DA_7 0x4E4 Read only Destination address for DMA channel 7
CC_0 0x408 Read only Channel control for DMA channel 0
CC_1 0x428 Read only Channel control for DMA channel 1
CC_2 0x448 Read only Channel control for DMA channel 2
CC_3 0x468 Read only Channel control for DMA channel 3
CC_4 0x488 Read only Channel control for DMA channel 4
CC_5 0x4A8 Read only Channel control for DMA channel 5
CC_6 0x4C8 Read only Channel control for DMA channel 6
CC_7 0x4E8 Read only Channel control for DMA channel 7
LC0_0 0x40C Read only Loop counter for DMA channel 0
LC0_1 0x42C Read only Loop counter for DMA channel 1
LC0_2 0x44C Read only Loop counter for DMA channel 2
LC0_3 0x46C Read only Loop counter for DMA channel 3
LC0_4 0x48C Read only Loop counter for DMA channel 4
LC0_5 0x4AC Read only Loop counter for DMA channel 5
LC0_6 0x4CC Read only Loop counter for DMA channel 6
LC0_7 0x4EC Read only Loop counter for DMA channel 7
LC1_0 0x410 Read only Loop counter 1 for DMA channel 0
LC1_1 0x430 Read only Loop counter 1 for DMA channel 1
LC1_2 0x450 Read only Loop counter 1 for DMA channel 2
LC1_3 0x470 Read only Loop counter 1 for DMA channel 3
LC1_4 0x490 Read only Loop counter 1 for DMA channel 4
LC1_5 0x4B0 Read only Loop counter 1 for DMA channel 5
LC1_6 0x4D0 Read only Loop counter 1 for DMA channel 6
LC1_7 0x4F0 Read only Loop counter 1 for DMA channel 7
DBGSTATUS 0xD00 Read only Debug status register
DBGCMD 0xD04 Read only Debug command register
DBGINST0 0xD08 Read only Debug instruction-0 register
DBGINST1 0xD0C Read only Debug instruction-1 register
periph_id_0 0xFE0 Read only Peripheral ID register 0
periph_id_1 0xFE4 Read only Peripheral ID register 1
periph_id_2 0xFE8 Read only Peripheral ID register 2
periph_id_3 0xFEC Read only Peripheral ID register 3
pcell_id_0 0xFF0 Read only PrimeCell ID register 0
pcell_id_1 0xFF4 Read only PrimeCell ID register 1
pcell_id_2 0xFF8 Read only PrimeCell ID register 2
pcell_id_3 0xFFC Read only PrimeCell ID register 3

PL330_DMAC - verification and testing

The functions of this component have been tested individually using a tailored test suite.

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