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PL350_SMC component

This section describes the PL350_SMC component.

PL350_SMC - about

This LISA+ component is a model of the ARM® PrimeCell Static Memory Controller (PL350).

It provides two memory interfaces. Each interface can be connected to a maximum of four memory devices, giving a total of eight inputs from the PVBusDecoder and eight outputs to either SRAM or NAND devices. Only one kind of memory can be connected to a particular interface, either SRAM or NAND.

This component provides a PVBus slave to control the device behavior. A remap port is also provided to assist in remapping particular memory regions.

PL350_SMC - ports

This section describes the ports.

Table 4-130 PL350_SMC ports

Name Protocol Type Description
axi_chip_if0_in[4] PVBus Slave Slave bus for interface 0 connecting to memory
axi_chip_if1_in[4] PVBus Slave Slave bus for interface 1 PVBus connecting to memory
apb_interface PVBus Slave Slave bus interface for register access
axi_chip_if0_out[4] PVBus Master Master interface 0 to connect to SRAM/NAND
axi_chip_if1_out[4] PVBus Master Master interface 1 to connect to SRAM/NAND
axi_remap PVBus Slave Remaps the device to 0x0
irq_in_if0 Signal Slave Interface 0 interrupt connection from the device
irq_in_if1 Signal Slave Interface 1 interrupt connection from the device
nand_remap_port PVBus Slave Remaps the connected NAND port to 0x0
irq_out Signal Master Interrupt port

PL350_SMC - parameters

This section describes the parameters.

Table 4-131 PL350_SMC parameters

Name Type Allowed values Default value Description

IF0_MEM_TYPE_PARAMETER

IF1_MEM_TYPE_PARAMETER

Integer 0, 1 0

Memory type for interfaces 0 and 1:

0
SRAM.
1
NAND.
REMAP Integer -1, 0-7 -1

If an interface is remapped:

-1
Remap not enabled.
0 to 7
Device that gets address 0x0.

IF0_CHIP_0 to IF0_CHIP_3

IF1_CHIP_0 to IF1_CHIP_3

Boolean true, false false

Memory connected to chip slots for interfaces 0 and 1:

true
Nothing connected.
false
Memory connected.

IF0_CHIP0_BASE to IF0_CHIP3_BASE

IF1_CHIP0_BASE to IF1_CHIP3_BASE

Integer Address where chips connected 0

Chip y base address for interfaces 0 and 1.

IF0_CHIP0_SIZE to IF0_CHIP3_SIZE

IF1_CHIP0_SIZE to IF1_CHIP3_SIZE

Integer Device size 0

Chip y size for interfaces 0 and 1.

PL350_SMC - registers

This section describes the registers.

You can access the configuration registers through the APB interface.

Table 4-132 PL350_SMC registers

Name Offset Access Description
memc_status 0x000 Read only Memory controller status register
memif_cfg 0x004 Read only Memory interface configuration register
memc_cfg_set 0x008 Write only Set memory controller configurations.
memc_cfg_clr 0x00C Write only Clear the configuration register.
direct_cmd 0x010 Write only Commands sent to the device
set_cycles 0x014 Write only Holding register for cycle settings
set_opmode 0x018 Write only Holding register for opmode settings
refresh_period_0 0x020 Read/write Insert idle cycles on interface 0.
refresh_period_1 0x024 Read/write Insert idle cycles on interface 1.
device_cycles0_0 0x100 Read only Device cycle configuration
device_cycles0_1 0x120 Read only Device cycle configuration
device_cycles0_2 0x140 Read only Device cycle configuration
device_cycles0_3 0x160 Read only Device cycle configuration
device_cycles1_0 0x180 Read only Device cycle configuration
device_cycles1_1 0x1A0 Read only Device cycle configuration
device_cycles1_2 0x1C0 Read only Device cycle configuration
device_cycles1_3 0x1E0 Read only Device cycle configuration
opmode0_0 0x104 Read only Opmode configuration
opmode0_1 0x124 Read only Opmode configuration
opmode0_2 0x144 Read only Opmode configuration
opmode0_3 0x164 Read only Opmode configuration
opmode1_0 0x184 Read only Opmode configuration
opmode1_1 0x1A4 Read only Opmode configuration
opmode1_2 0x1C4 Read only Opmode configuration
opmode1_3 0x1E4 Read only Opmode configuration
user_status 0x200 Read/write User status register
user_config 0x204 Read/write User configuration register
periph_id_0 0xFE0 Read only Peripheral ID register 0a
periph_id_1 0xFE4 Read only Peripheral ID register 1a
periph_id_2 0xFE8 Read only Peripheral ID register 2a
periph_id_3 0xFEC Read only Peripheral ID register 3a
pcell_id_0 0xFF0 Read only PrimeCell ID register 0a
pcell_id_1 0xFF4 Read only PrimeCell ID register 1a
pcell_id_2 0xFF8 Read only PrimeCell ID register 2a
pcell_id_3 0xFFC Read only PrimeCell ID register 3a

PL350_SMC - verification and testing

The functions of this component have been tested individually using a tailored test suite.

PL350_SMC - performance

This component is optimized to have negligible impact on transaction performance, except when memory remap settings are changed when there might be a significant effect.

a This register has no CADI interface.
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