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SP810_SysCtrl component

This section describes the SP810_SysCtrl component.

SP810_SysCtrl - about

This LISA+ component is a model of the PrimeXsys System Controller (SP810).

SP810_SysCtrl - ports

This section describes the ports.

Table 4-158 SP810_SysCtrl ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock input
hclkdivsela ValueState Master Define the processor clock/bus clock ratio.
npora Signal Slave Power on reset
pll_ena Signal Master PLL enable output
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
ref_clk_in ClockSignal Slave Clock source used by the Timer and Watchdog modules.
sleep_modea Signal Master Control clocks for SLEEP mode.
timer_clk_en[0] ClockRateControl Master Timer clock enable 0
timer_clk_en[1] ClockRateControl Master Timer clock enable 1
timer_clk_en[2] ClockRateControl Master Timer clock enable 2
timer_clk_en[3] ClockRateControl Master Timer clock enable 3
remap_clear StateSignal Master Remap clear request output
remap_stata StateSignal Slave Remap status input
sys_modea ValueState Slave Present system mode
sys_stata ValueState Slave System status input
wd_clk_ena Signal Master Watchdog module clock enable output
wd_ena Signal Slave Watchdog module enable input

SP810_SysCtrl - parameters

This section describes the parameters.

Table 4-159 SP810_SysCtrl parameters

Name Type Allowed values Default value Description
sysid int - 0x00000000 System identification register.
use_s8 bool true, false false Enable switch S8.

SP810_SysCtrl - registers

This section describes the registers.

Table 4-160 SP810_SysCtrl registers

Name Offset Access Description
SCCTRL 0x0 Read/write System control
SCSYSSTAT 0x4 Read/write System status
SCIMCTRL 0x8 Read/write Interrupt mode control
SCIMSTAT 0xC Read/write Interrupt mode status
SCXTALCTRL 0x10 Read/write Crystal control
SCPLLCTRL 0x14 Read/write PLL control
SCPLLFCTRL 0x18 Read/write PLL frequency control
SCPERCTRL0 0x1C Read/write Peripheral control
SCPERCTRL1 0x20 Read/write Peripheral control
SCPEREN 0x24 Write only Peripheral clock enable
SCPERDIS 0x28 Write only Peripheral clock disable
SCPERCLKEN 0x2C Read only Peripheral clock enable status
SCPERSTAT 0x30 Read only Peripheral clock status
SCSysID0 0xEE0 Read only System identification 0
SCSysID1 0xEE4 Read only System identification 1
SCSysID2 0xEE8 Read only System identification 2
SCSysID3 0xEEC Read only System identification 3
SCITCR 0xF00 Read/write Integration test control
SCITIR0 0xF04 Read/write Integration test input 0
SCITIR1 0xF08 Read/write Integration test input 1
SCITOR 0xF0C Read/write Integration test output
SCCNTCTRL 0xF10 Read/write Counter test control
SCCNTDATA 0xF14 Read/write Counter data
SCCNTSTEP 0xF18 Write only Counter step
SCPeriphID0 0xFE0 Read only Peripheral identification 0
SCPeriphID1 0xFE4 Read only Peripheral identification 1
SCPeriphID2 0xFE8 Read only Peripheral identification 2
SCPeriphID3 0xFEC Read only Peripheral identification 3
SPCellID0 0xFF0 Read only PrimeCell identification 0
SPCellID1 0xFF4 Read only PrimeCell identification 1
SPCellID2 0xFF8 Read only PrimeCell identification 2
SPCellID3 0xFFC Read only PrimeCell identification 3
a Not fully implemented. Using this port has unpredictable results.