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SP810_SysCtrl component
This section describes the SP810_SysCtrl component.
SP810_SysCtrl - about
This LISA+ component is a model of the PrimeXsys System Controller (SP810).
SP810_SysCtrl - ports
This section describes the ports.
Table 4-158 SP810_SysCtrl ports
Name | Protocol | Type | Description |
---|---|---|---|
clk_in |
ClockSignal | Slave | Clock input |
hclkdivsel a |
ValueState | Master | Define the processor clock/bus clock ratio. |
npor a |
Signal | Slave | Power on reset |
pll_en a |
Signal | Master | PLL enable output |
pvbus |
PVBus | Slave | Slave port for connection to PV bus master/decoder |
ref_clk_in |
ClockSignal | Slave | Clock source used by the Timer and Watchdog modules. |
sleep_mode a |
Signal | Master | Control clocks for SLEEP mode. |
timer_clk_en[0] |
ClockRateControl | Master | Timer clock enable 0 |
timer_clk_en[1] |
ClockRateControl | Master | Timer clock enable 1 |
timer_clk_en[2] |
ClockRateControl | Master | Timer clock enable 2 |
timer_clk_en[3] |
ClockRateControl | Master | Timer clock enable 3 |
remap_clear |
StateSignal | Master | Remap clear request output |
remap_stat a |
StateSignal | Slave | Remap status input |
sys_mode a |
ValueState | Slave | Present system mode |
sys_stat a |
ValueState | Slave | System status input |
wd_clk_en a |
Signal | Master | Watchdog module clock enable output |
wd_en a |
Signal | Slave | Watchdog module enable input |
SP810_SysCtrl - parameters
This section describes the parameters.
Table 4-159 SP810_SysCtrl parameters
Name | Type | Allowed values | Default value | Description |
---|---|---|---|---|
sysid |
int |
- |
|
System identification register. |
use_s8 |
bool |
true , false |
false |
Enable switch S8. |
SP810_SysCtrl - registers
This section describes the registers.
Table 4-160 SP810_SysCtrl registers
Name | Offset | Access | Description |
---|---|---|---|
SCCTRL |
|
Read/write | System control |
SCSYSSTAT |
|
Read/write | System status |
SCIMCTRL |
|
Read/write | Interrupt mode control |
SCIMSTAT |
|
Read/write | Interrupt mode status |
SCXTALCTRL |
|
Read/write | Crystal control |
SCPLLCTRL |
|
Read/write | PLL control |
SCPLLFCTRL |
|
Read/write | PLL frequency control |
SCPERCTRL0 |
|
Read/write | Peripheral control |
SCPERCTRL1 |
|
Read/write | Peripheral control |
SCPEREN |
|
Write only | Peripheral clock enable |
SCPERDIS |
|
Write only | Peripheral clock disable |
SCPERCLKEN |
|
Read only | Peripheral clock enable status |
SCPERSTAT |
|
Read only | Peripheral clock status |
SCSysID0 |
|
Read only | System identification 0 |
SCSysID1 |
|
Read only | System identification 1 |
SCSysID2 |
|
Read only | System identification 2 |
SCSysID3 |
|
Read only | System identification 3 |
SCITCR |
|
Read/write | Integration test control |
SCITIR0 |
|
Read/write | Integration test input 0 |
SCITIR1 |
|
Read/write | Integration test input 1 |
SCITOR |
|
Read/write | Integration test output |
SCCNTCTRL |
|
Read/write | Counter test control |
SCCNTDATA |
|
Read/write | Counter data |
SCCNTSTEP |
|
Write only | Counter step |
SCPeriphID0 |
|
Read only | Peripheral identification 0 |
SCPeriphID1 |
|
Read only | Peripheral identification 1 |
SCPeriphID2 |
|
Read only | Peripheral identification 2 |
SCPeriphID3 |
|
Read only | Peripheral identification 3 |
SPCellID0 |
|
Read only | PrimeCell identification 0 |
SPCellID1 |
|
Read only | PrimeCell identification 1 |
SPCellID2 |
|
Read only | PrimeCell identification 2 |
SPCellID3 |
|
Read only | PrimeCell identification 3 |
a Not fully implemented. Using this port has
unpredictable results.