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ARM1176CT component

This section describes the ARM1176CT component.

ARM1176CT - about

This C++ component is a model of r0p4 of an ARM1176JZF-S™ processor.

ARM1176CT - ports

This section describes the ports.

Table 3-79 ARM1176CT ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock input
pvbus_m PVBus Master Master port for all memory accesses
reset Signal Slave Asynchronous reset signal input
irq Signal Slave Asynchronous IRQ signal input
fiq Signal Slave Asynchronous FIQ signal input
pmuirq Signal Master Performance monitoring unit IRQ output
dmairq Signal Master Normal DMA interrupt output
dmasirq Signal Master Secure DMA interrupt output
dmaexterrirq Signal Master DMA error interrupt output
vic_addr ValueState Slave Address input for connection to PL192 VIC
vic_ack Signal Master Acknowledge signal output for PL192 VIC
ticks InstructionCount Master Output that can be connected to a visualization component

ARM1176CT - parameters

This section describes the parameters.

Table 3-80 ARM1176CT parameters

Name Type Allowed values Default value Description
BIGENDINIT Boolean true, false false Initialize to ARMv5 big endian mode.
CP15SDISABLE Boolean true, false false Initialize to disable access to some CP15 registers.
INITRAM Boolean true, false false Initialize with ITCM0 enabled at address 0x0.
UBITINIT Boolean true, false false Initialize to ARMv6 unaligned behavior.
VINITHI Boolean true, false false Initialize with high vectors enabled.
itcm0_size Integer 0x00-0x40 0x10 Size of ITCM in KB.
dtcm0_size Integer 0x00-0x40 0x10 Size of DTCM in KB.
device-accurate-tlb Boolean true, false falsea Specify whether all TLBs are modeled.
semihosting-cmd_lineb String No limit except memory [Empty string] Command line available to semihosting SVC calls.
semihosting-enable Boolean true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-ARM_SVC Integer uint24_t 0x123456 A32 SVC number for semihosting.
semihosting-Thumb_SVC Integer uint8_t 0xAB T32 SVC number for semihosting.
semihosting-heap_base Integer 0x00000000-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit Integer 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base Integer 0x00000000-0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit Integer 0x00000000-0xFFFFFFFF 0x0F0000000 Virtual address of stack limit.
vfp-enable_at_resetc Boolean true, false false Enable coprocessor access and VFP at reset.
vfp-present Boolean true, false true Configure processor as VFP enabled.d
cpi_mul Integer 1-0x7FFFFFFF 1 Multiplier for calculating Cycles Per Instruction (CPI).
cpi_div Integer 1-0x7FFFFFFF 1 Divider for calculating CPI.

ARM1176CT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the coprocessor 14 registers and the integration and test registers.

This PV model does not model Level 1 or Level 2 caches. The system coprocessor registers related to cache operations permit cache aware software to work, but in most cases they only check register access permissions:

  • Cache behavior override.
  • Cache Dirty Status.
  • Invalidate and/or Clean Both Caches.
  • Invalidate and/or Clean Entire ICache/DCache.
  • Invalidate and/or Clean ICache/DCache by Index.
  • Invalidate and/or Clean ICache/DCache by MVA.
  • Data Write Barrier.
  • Data Memory Barrier.
  • Prefetch ICache Line.
  • ICache/DCache lockdown.
  • ICache/DCache master valid.

TLBs

These TLB registers do not have working implementations:

  • Normal memory remap register.
  • Primary memory remap register.
  • TLB Lockdown Attr.
  • TLB Lockdown Index.
  • TLB Lockdown PA.
  • TLB Lockdown VA.

In addition, the simulation does not distinguish peripheral accesses from data accesses, so it ignores configuration of the peripheral port memory remap register.

ARM1176CT - debug features

This component exports a CADI debug interface.

ARM1176CT - debug - registers

All core, VFP, and CP15 registers are visible in the debugger.

The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior.

ARM1176CT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARM1176CT - debug - memory

This component presents two 4GB views of virtual memory, one as seen from secure mode and one as seen from normal mode.

ARM1176CT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of Linux on an example system.

ARM1176CT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

There is a single memory port combining instruction, data, and peripheral access.

a

Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.

b

The value of argv[0] points to the first command line argument, not to the name of an image.

c

This is model specific behavior with no hardware equivalent.

d

This parameter lets you disable the VFP features of the model. However the model has not been validated as a true ARM1176JZ-S processor.

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