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ARM968CT component

This section describes the ARM968CT component.

ARM968CT - about

This C++ component is a model of r0p1 of an ARM968E-S™ processor.

ARM968CT - ports

This section describes the ports.

Table 3-83 ARM968CT ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock input
pvbus_m PVBus Master Master port for all memory accesses
reset Signal Slave Asynchronous reset signal input
irq Signal Slave Asynchronous IRQ signal input
fiq Signal Slave Asynchronous FIQ signal input
ticks InstructionCount Master Output that can be connected to a visualization component
vinithi Signal Slave Initialize with high vectors enabled after a reset
initram Signal Slave Initialize with ITCM enabled after reset
itcm PVBus Slave Slave access to ITCM
dtcm PVBus Slave Slave access to DTCM
bigendinit Signal Slave Enable BE32 endianness after reset

ARM968CT - parameters

This section describes the parameters.

Table 3-84 ARM968CT parameters

Name Type Allowed values Default value Description
BIGENDINIT Boolean true, false false Initialize to ARMv5 big endian mode.
INITRAM Boolean true, false false Initialize with ITCM0 enabled at address 0x0.
VINITHI Boolean true, false false Initialize with high vectors enabled.
dtcm0_size Integer 0x0000-0x1000 0x8 Size of DTCM in KB, 0 disables.
itcm0_size Integer 0x0000-0x1000 0x8 Size of ITCM in KB, 0 disables.
master_id Integer 0x0000-0xFFFF 0x0 Master ID presented in bus transactions.
semihosting-ARM_SVC Integer uint24_t 0x123456 A32 SVC number for semihosting.
semihosting-Thumb_SVC Integer uint8_t 0xAB T32 SVC number for semihosting.
semihosting-cmd_linea String No limit except memory [Empty string] Command line available to semihosting SVC calls.
semihosting-enable Boolean true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-heap_base Integer 0x00000000-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit Integer 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base Integer 0x00000000-0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit Integer 0x00000000-0xFFFFFFFF 0x0F0000000 Virtual address of stack limit.
cpi_mul Integer 1-0x7FFFFFFF 1 Multiplier for calculating Cycles Per Instruction (CPI).
cpi_div Integer 1-0x7FFFFFFF 1 Divider for calculating CPI.

ARM968CT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the coprocessor 14 registers and the integration and test registers.

ARM968CT - debug features

This component exports a CADI debug interface.

ARM968CT - debug - registers

All core and CP15 registers are visible in the debugger.

The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior.

ARM968CT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARM968CT - debug - memory

This component presents a single flat 4GB view of virtual memory as seen by the processor.

ARM968CT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of uClinux and ThreadX OS on an example system.

ARM968CT - performance

This component provides high performance in all areas except when protection regions are configured with regions or subregions less than 1KB in size. Any execution of instructions within the aligned 1KB of memory containing that region runs slower than expected.

ARM968CT - DMA

Enable the DMA to or from TCMs by connecting the TCM ports to a standard PVBusDecoder. The ARM968CT or any other master can access the TCMs.

The TCM regions do not behave exactly as described in the technical reference manual.

  • DTCM1 is not supported.
  • TCM memory does not alias throughout the 4MB TCM regions, only the lowest mapping can be used to access the TCMs. Aliasing can be implemented by appropriate mapping on the PVBusDecoder.
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The value of argv[0] points to the first command line argument, not to the name of an image.

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