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ARMCortexM0CT component

This section describes the ARMCortexM0CT component.

ARMCortexM0CT - about

This C++ component models r0p0 of a Cortex®-M0 core.

This model does not have a parameter that is equivalent to the RAR integration option. The architecturally required register state is reset.

ARM does not guarantee that all ARMv7-M behavior is absent from models of ARMv6-M cores. As a consequence, ARM does not guarantee that code that runs on ARMv7-M cores but fails on ARMv6-M cores fails on ARMv6-M Fast Models cores.

ARMCortexM0CT - ports

This section describes the ports.

Table 3-77 ARMCortexM0CT ports

Name Protocol Type Description
auxfault Value Slave This port is wired to the Auxiliary Fault Status Register.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
currpri Value Master Current execution priority.
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
intisr[32] Signal Slave This signal array delivers signals to the NVIC.
intnmi Signal Slave Configure nonmaskable interrupt.
lockup Signal Master Asserted when the processor is in lockup state.
poreset Signal Slave Raising this signal will do a power-on reset of the core.
stcalib Value Slave The calibration value for the SysTick timer.
stclk ClockSignal Slave The reference clock for the SysTick timer.
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
sysreset Signal Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.

ARMCortexM0CT - parameters

This section describes the parameters.

Table 3-78 ARMCortexM0CT parameters

Name Type Allowed values Default value Description
BIGENDINIT bool true, false false Initialize processor to big endian mode.
BKPT uint32_t 0x0-0x4 0x4 The number of breakpoint unit comparators. Runtime parameter.
cpi_div uint32_t 0x1-0x7FFFFFFF 0x1 Divider for calculating CPI (Cycle Per Instruction). Runtime parameter.
cpi_mul uint32_t 0x1-0x7FFFFFFF 0x1 Multiplier for calculating CPI (Cycle Per Instruction). Runtime parameter.
DBG bool true, false true Whether or not the debug extensions are implemented.
master_id uint32_t 0x0-0xFFFFFFFF 0x0 Master ID presented in bus transactions.
min_sync_level uint32_t 0x0-0x3 0x0 Force minimum syncLevel (0 = off = default,1 = syncState, 2 = postInsnIO, 3 = postInsnAll). Runtime parameter.
NUM_IRQ uint32_t 0x1-0x20 0x20 Number of user interrupts.
semihosting-cmd_line string - "" Command line available to semihosting SVC calls.
semihosting-cwd string - "" Virtual address of CWD.
semihosting-enable bool true, false true Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base uint32_t 0x0-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit uint32_t 0x0-0xFFFFFFFF 0x10700000 Virtual address of top of heap.
semihosting-stack_base uint32_t 0x0-0xFFFFFFFF 0x10700000 Virtual address of base of descending stack.
semihosting-stack_limit uint32_t 0x0-0xFFFFFFFF 0x10800000 Virtual address of stack limit.
semihosting-Thumb_SVC uint32_t 0x0-0xFFFFFFFF 0xAB T32 SVC number for semihosting.
SYST bool true, false true Include SysTick timer functionality.
WIC bool true, false true Include support for WIC-mode deep sleep.
WPT uint32_t 0x0-0x2 0x2 The number of watchpoint unit comparators. Runtime parameter.
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