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ARMCortexM4CT component

This section describes the ARMCortexM4CT component.

ARMCortexM4CT - about

This C++ component is a model of r0p0 of a Cortex®-M4 processor.

ARMCortexM4CT - ports

This section describes the ports.

Table 3-71 ARMCortexM4CT ports

Name Protocol Type Description
auxfault Value Slave Auxiliary fault status information.
bigend Signal Slave Configure endianness after a reset.
clk_in ClockSignal Slave Clock input.
currpri Value Master Current execution priority of the processor.
edbgrq Signal Master External debug request.
event Signal Peer Event input and output for wakeup from WFE. This port combines the TXEV and RXEV signals.
intisr[0-239] Signal Slave External interrupt signals.
intnmi Signal Slave Nonmaskable interrupt.
lockup Signal Master Asserted when processor is in lockup state.
poreset Signal Slave Asynchronous power-on reset signal input.
pvbus_m PVBus Master Master port for all memory accesses except those on the External Private Peripheral Bus.
pv_ppbus_m PVBus Master Master port for memory accesses on the External Private Peripheral Bus.
reset Signal Slave Asynchronous reset signal input (not debug components).
sleepdeep Signal Master Processor is in deep sleep.
sleeping Signal Master Processor is in sleep.
stcalib Value Slave SysTick calibration value.
stclk ClockSignal Slave Reference clock input for SysTick.
sysreset Signal Slave Asynchronous reset signal input.
sysresetreq Signal Master System reset request.
ticks InstructionCount Master Output that can be connected to a visualization component.
dbgena Signal Slave Enable hardware debugger access.
fpudisable Signal Slave Disable FPU on next reset.
mpudisable Signal Slave Disable MPU on next reset.
fpxxc Value Master Cumulative exception flags from the Floating Point Status and Control Register (FPSCR). This value port combines the five RTL signals FPIXC, FPIDC, FPOFC, FPUFC, FPDZC, and FPIOC.

ARMCortexM4CT - parameters

This section describes the parameters.

Table 3-72 ARMCortexM4CT parameters

Name Type Allowed values Default value Description
BB_PRESENT Boolean true, false true Enable bitbanding.
BIGENDINIT Boolean true, false false Initialize processor to big endian mode.
LVL_WIDTH Integer 3-8 3 Number of bits of interrupt priority.
NUM_IRQ Integer 1-240 16 Number of user interrupts.
NUM_MPU_REGION Integer 0, 8 8 Number of MPU regions.
master_id Integer 0x0000-0xFFFF 0x0 Master ID presented in bus transactions.
min_sync_level Integer 0-3 0 Controls the minimum syncLevel.
semihosting-Thumb_SVC Integer 8-bit integer 0xAB T32 SVC number for semihosting.
semihosting-cmd_line String No limit except memory [Empty string] Command line available to semihosting SVC calls.
semihosting-enable Boolean true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-heap_base Integer 0x00000000-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit Integer 0x00000000-0xFFFFFFFF 0x10700000 Virtual address of top of heap.
semihosting-stack_base Integer 0x00000000-0xFFFFFFFF 0x10700000 Virtual address of base of descending stack.
semihosting-stack_limit Integer 0x00000000-0xFFFFFFFF 0x10800000 Virtual address of stack limit.
vfp-present Boolean true, false true Set whether the model has VFP support.
cpi_mul Integer 1-0x7FFFFFFF 1 Multiplier for calculating Cycles Per Instruction (CPI).
cpi_div Integer 1-0x7FFFFFFF 1 Divider for calculating CPI.

ARMCortexM4CT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the processor debug registers, system debug registers, debug interface port registers, TPIU registers, and ETM registers.

ARMCortexM4CT - caches

This component does not implement any caches.

ARMCortexM4CT - debug features

This component exports a CADI debug interface.

ARMCortexM4CT - debug - registers

All core and implemented registers are visible in the debugger.

ARMCortexM4CT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexM4CT - debug - memory

This component presents one 4GB view of virtual memory.

ARMCortexM4CT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of uClinux on an example system.

ARMCortexM4CT - performance

This component provides high performance in all areas except with instructions in protection regions smaller than 1KB, and FP instruction set execution.

ARMCortexM4CT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • The Wakeup Interrupt Controller (WIC) is not implemented.
  • Power control is not implemented. Powering down of the processor is not supported. The processor must still be clocked even if it has asserted the sleeping or sleepdeep signals.
  • Only the minimal level of debug support is provided (no DAP, FPB, DWT or halting debug capability).
  • No debug-related components are implemented.
  • The unimplemented registers are the processor debug registers, system debug registers, debug interface port registers, TPIU registers, and ETM registers.
  • No trace support (no ETM, ITM, TPUI or HTM).
  • There is no supported equivalent of the RESET_ALL_REGS configuration setting in RTL (that forces all registers to have a well defined value on reset).
  • Disabling processor features using the Auxiliary Control Register is not supported.
  • Only a single pvbus_m master port is provided. This combines the ICode, DCode and System bus interfaces of the RTL. The external PPB bus is provided by the pv_ppbus_m master port.
  • In privileged mode, STRT and LDRT to the PPB region are not forbidden access.
  • The RTL implements the ROM table as an external component on the External Private Peripheral Bus. In the CT model the ROM table is implemented internally as a fallback if an external PPB access in the ROM table address region aborts. This permits the default ROM table to be overridden (by implementing an external component connected to the external PPB to handle accesses to these addresses) without requiring every user of the processor to implement and connect a ROM table component.

Since the CT model does not provide a DAP port or halting debug capability, this signal is ignored.