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VE memory map for Cortex-A series

The Versatile Express RS1 memory map with the RS2 extensions is the base of the global memory map for the Cortex-A series platform model.

Note

The VE FVP implementation of memory does not require the memory controller to have the correct values. If you run applications on actual hardware, ensure that the memory controller is set up properly so that they run properly.

Table 7-1 Cortex-A series platform model memory map

Name Modeled Address range Size
NOR FLASH0 (CS0) Yes 0x00_00000000-0x00_03FFFFFF 64MB
Reserved - 0x00_04000000-0x00_07FFFFFF 64MB
NOR FLASH0 alias (CS0) Yes 0x00_08000000-0x00_0BFFFFFF 64MB
NOR FLASH1 (CS4) Yes 0x00_0C000000-0x00_0FFFFFFF 64MB
Unused (CS5) - 0x00_10000000-0x00_13FFFFFF -
PSRAM (CS1) - unused No 0x00_14000000-0x00_17FFFFFF -
Peripherals (CS2). See below. Yes 0x00_18000000-0x00_1BFFFFFF 64MB
Peripherals (CS3). See below. Yes 0x00_1C000000-0x00_1FFFFFFF 64MB
CoreSight and peripherals No 0x00_20000000-0x00_2CFFFFFFa -
Graphics space No 0x00_2D000000-0x00_2D00FFFF -
System SRAM Yes 0x00_2E000000-0x00_2EFFFFFF 64KB
Ext AXI No 0x00_2F000000-0x00_7FFFFFFF -
4GB DRAM (in 32-bit address space)b Yes 0x00_80000000-0x00_FFFFFFFF 2GB
Unused - 0x01_00000000-0x07_FFFFFFFF -
4GB DRAM (in 36-bit address space)b Yes 0x08_00000000-0x08_FFFFFFFF 4GB
Unused - 0x09_00000000-0x7F_FFFFFFFF -
4GB DRAM (in 40-bit address space)b Yes 0x80_00000000-0xFF_FFFFFFFF 4GB

The model has a secure_memory option. When you enable this option, the memory map changes for a number of peripherals.

Table 7-2 CS2 region peripheral memory map for secure_memory option

Peripheral Address range Functionality with secure_memory enabled
NOR FLASH0 (CS0) 0x00_00000000-0x00_0001FFFF Secure RO, aborts on non-secure accesses.
Reserved 0x00_04000000-0x00_0401FFFF Secure SRAM, aborts on non-secure accesses.
NOR FLASH0 alias (CS0) 0x00_08000000-0x00_7DFFFFFF Normal memory map, aborts on secure accesses.
Ext AXI 0x00_7e000000-0x00_7FFFFFFF Secure DRAM, aborts on non-secure accesses.
4GB DRAM (in 32-bit address space) 0x00_80000000-0xFF_FFFFFFFF Normal memory map, aborts on secure accesses.

Table 7-3 CS2 region peripheral memory map

Peripheral Modeled Address range Size GIC Int
VRAM - aliased Yes 0x00_18000000-0x00_19FFFFFF 32MB -
Ethernet (SMSC 91C111) Yes 0x00_1A000000-0x00_1AFFFFFF 16MB 47
USB - unused No 0x00_1B000000-0x00_1BFFFFFF 16MB -

Table 7-4 CS3 region peripheral memory map

Peripheral Modeled Address range Size GIC Int
Local DAP ROM No 0x00_1C000000-0x00_1C00FFFF 64KB -
VE System Registers Yes 0x00_1C010000-0x00_1C01FFFF 64KB -
System Controller (SP810) Yes 0x00_1C020000-0x00_1C02FFFF 64KB -
TwoWire serial interface (PCIe) No 0x00_1C030000-0x00_1C03FFFF 64KB -
AACI (PL041) Yes 0x00_1C040000-0x00_1C04FFFF 64KB 43
MCI (PL180) Yes 0x00_1C050000-0x00_1C05FFFF 64KB 41, 42
KMI - keyboard (PL050) Yes 0x00_1C060000-0x00_1C06FFFF 64KB 44
KMI - mouse (PL050) Yes 0x00_1C070000-0x00_1C07FFFF 64KB 45
Reserved - 0x00_1C080000-0x00_1C08FFFF 64KB -
UART0 (PL011) Yes 0x00_1C090000-0x00_1C09FFFF 64KB 37
UART1 (PL011) Yes 0x00_1C0A0000-0x00_1C0AFFFF 64KB 38
UART2 (PL011) Yes 0x00_1C0B0000-0x00_1C0BFFFF 64KB 39
UART3 (PL011) Yes 0x00_1C0C0000-0x00_1C0CFFFF 64KB 40
VFS2 Yes 0x00_1C0D0000-0x00_1C0DFFFF 64KB 73
Reserved - 0x00_1C0E0000-0x00_1C0EFFFF 64KB -
Watchdog (SP805) Yes 0x00_1C0F0000-0x00_1C0FFFFF 64KB 32
Reserved - 0x00_1C100000-0x00_1C10FFFF 64KB -
Timer-0 (SP804) Yes 0x00_1C110000-0x00_1C11FFFF 64KB 34
Timer-1 (SP804) Yes 0x00_1C120000-0x00_1C12FFFF 64KB 35
Reserved - 0x00_1C130000-0x00_1C15FFFF 192KB -
TwoWire serial interface (DVI) - unused No 0x00_1C160000-0x00_1C16FFFF 64KB -
Real-time Clock (PL031) Yes 0x00_1C170000-0x00_1C17FFFF 64KB 36
Reserved - 0x00_1C180000-0x00_1C19FFFF 128KB -
CF Card - unused No 0x00_1C1A0000-0x00_1C1AFFFF 64KB  
Reserved - 0x00_1C1B0000-0x00_1C1EFFFF 256KB -
Color LCD Controller (PL111) Yes 0x00_1C1F0000-0x00_1C1FFFFF 64KB 46
Reserved - 0x00_1C200000-0x00_1FFFFFFF 64KB -
a The private peripheral region address 0x2c000000 is mapped in this region. You can use the parameter PERIPHBASE to map the peripherals to a different address.
b The model contains only 4GB of DRAM. The DRAM memory address space is aliased across the three different regions and where the mapped address space is greater than 4GB.
c Use these interrupt signal values to program your interrupt controller. They are the SPI number plus 32. Add 32 to the interrupt numbers from the peripherals to form the interrupt number that the GIC sees. GIC interrupts 0-31 are for internal use.
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