4.4.8 CCI500 component
This section describes the CCI500 component.
CCI500 - about
This C++ component is a model of r0p0 of the CCI-500 Cache Coherent Interconnect for AXI4.
AXI Coherency Extensions (ACE) are extensions to AXI4. They support system-level cache-coherency between multiple clusters.
CCI500 - functionality
Some features differ in the model.
- Address Decoder
-
- Only supports striping down to 4KiB.
- If the address decoder aborts the access, returns
SLVERR
rather thanDECERR
.
- Interfaces
- The model does not implement the Q-Channel and P-Channel interfaces.
- Performance Monitoring Unit
-
- PMU counters recognize only a few event sources:
- Slave interface events:
3 ReadOnce. 4 ReadClean, ReadShared, ReadNotSharedDirty, ReadUnique. 5 MakeUnique, CleanUnique. 6 CleanInvalid, CleanShared, MakeInvalid. 7 DVM transaction received from upstream. 9 Read data that is satisfied by a snoop request. - No events are implemented for the global events or for the master events.
- Slave interface events:
- The PMU does not implement the event bus (
EVNTBUS
).
- PMU counters recognize only a few event sources:
- Register access
- The register file only supports 32-bit accesses to its registers. Later versions of the CCI500 hardware support full write strobes to the register file. This limitation means that byte and halfword accesses work on the hardware but not on this version of the component.
- Snoop filter RAMs
- Snoop filter RAMs are not modelled. The Status Register fields that relate to the power state of the Snoop filter RAMs are undefined.
CCI500 - ports
This section describes the ports.
acchannelens
represents the ports x
ACCHANNELENS0
-ACCHANNELENS6
on the RTL (Register Transfer Level) (assuming that there are seven upstream
ports).
- Each upstream ACE port
y
(pvbus_s[
) has a two bity
]ACCHANNELENS
.x
- Bit 0 == 0
- disables DVM messages from being sent to this interface.
- Bit 1 == 0
- disables snoop messages from being sent to this interface.
- Each upstream ACE-Lite port
z
(pvbus_s[
) has a one bitz
]ACCHANNELENS
.x
- Bit 0 == 0
- disables DVM messages from being sent to this interface.
The model supports various configurations with one LISA file. Each channel enable behaves as though it is one bit or two bit, as appropriate. If you send an invalid value, because of the type of the port, then the CCI model halts, producing a fatal error. Parameters set the initial values until you drive them, so if they are constant then you need not drive them.
In the RTL, the CCI500 samples the signals at reset. In the model, the CCI500 samples the signals at the first transaction. Thus any controller that produces these signals has to hold them constant for long enough.
Table 4-37 CCI500 ports
Name | Protocol | Type | Description |
---|---|---|---|
acchannelens |
Value | Slave | - |
evntcntoverflow[8] |
Signal | Master | - |
reset_state_of_upstream_port[7] |
Signal | Slave | - |
pvbus_register_file_s |
PVBus | Slave | - |
pvbus_s[7] |
PVBus | Slave | - |
pvbus_m[6] |
PVBus | Master | - |
errirq |
Signal | Master | - |
dbgen |
Signal | Slave | - |
spiden |
Signal | Slave | - |
spniden |
Signal | Slave | - |
niden |
Signal | Slave | - |
address_decoder |
CCI500_AddressDecoderProtocol | Master | - |
CCI500 - parameters
This section describes the parameters.
The LISA file declares seven upstream ports. You can configure these ports with
num_ace_ports
and num_ace_lite_ports
. The bottom
num_ace_lite_ports
are ACE-Lite+DVM. The next
num_ace_ports
are ACE. Any remaining ports are ignored; if transactions
are made on them, then warnings are produced. For example, if num_ace_ports
= 1 and num_ace_lite_ports
= 1 then pvbus_s[1]
is ACE,
pvbus_s[0]
is ACE-Lite+DVM and pvbus_s[6-2]
are
considered not to exist.
Table 4-38 CCI500 parameters
Name | Type | Allowed values | Default value | Description |
---|---|---|---|---|
cache_state_modelled |
bool |
true , false |
true |
Model the cache state. |
num_ace_ports |
unsigned |
1 -4 |
2 |
The top num_ace_ports are ACE and
support full coherency. The total number of ports must not exceed seven. |
num_ace_lite_ports |
unsigned |
1 -6 |
5 |
The number of ACE-Lite+DVM ports. These ports are the lowest numbered ports. The total number of ports must not exceed seven. |
acchannelens |
uint64_t |
-
|
|
For upstream port
pvbus_s[ , where 0 <=
n <= 6 . Bit[0] == 0
disables DVM messages from being sent. If this port is an ACE port, then bit[1] ==
0 disables snoop messages from being sent. The signal
acchannelens can
override this parameter. For an ACE-Lite port, bit[1] from the parameter is ignored,
allowing the default value of to create a functional system without
excessive configuration. |
dbgen |
bool |
true , false |
true |
Invasive debug enable. If true ,
enables the counting of PMU events. |
spiden |
bool |
true , false |
true |
Secure invasive debug enable. If both
SPIDEN and DBGEN are high, enables the counting
of both Non-secure and Secure events. |
spniden |
bool |
true , false |
true |
Whether Secure and Non-secure events are allowed to be counted in the performance monitor. |
niden |
bool |
true , false |
true |
Whether Non-secure events are allowed to be counted in the performance monitor. |
force_on_from_start |
bool |
true , false |
false |
The interconnect normally starts up with snooping
disabled. This parameter allows the model to start up as enabled without programming
it. This enabling is only set up at simulation reset and not at signal reset. If the
upstreams can ever be held in reset, then connect the reset_state_of_upstream_port ports so that the CCI knows when to disable
snoops to the upstream systems. Otherwise, the upstream system complains that it "received a snoop request while it was in reset". |
reentrancy_support |
string |
- | "env " |
Must be one of: on ,
off , cacheglobal , env .
on : hazard checking per cache line (normal mode).
off : no hazard checking (use only for single master systems).
cacheglobal : hazard checking globally for cache (not per cache
line, testing feature, provokes more hazards than necessary). env
(or empty string): take value from FM_REENTRANCY_SUPPORT env var;
if this env var is not set, use on . |
number_of_phantom_entries |
uint64_t |
|
|
Number of phantom entries in the cache. Certain cache operations use phantom entries to hold temporary data. The default value is safe for all systems containing up to 32 masters. |
version |
string |
- | "" | The version of the interconnect. Allowed versions:
r0p0 . |