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4.4.29 MemoryMappedCounterModule component

This section describes the MemoryMappedCounterModule component.

MemoryMappedCounterModule - about

This LISA+ component is a model of a memory mapped counter module.

It is essential for multiple clusters of cores with Generic Timers, and also for single core systems where the Generic Timer runs at a different rate to the input clock to the core.

MemoryMappedCounterModule - ports

This section describes the ports.

Note

The component has two bus slave ports because the architecture specification permits you to map each set of registers at different, noncontiguous base addresses.

Table 4-80 MemoryMappedCounterModule ports

Name Protocol Type Description
clk_in Clock signal Slave This clock input determines the frequency of the Physical Count provided to the clusters connected to the cntvalueb port.
cntvalueb CounterInterface Master This master port implements a private protocol between the cluster and the MemoryMappedCounterModule. Connect this port to the cntvalueb port on each cluster in the system and to the MemoryMappedCounterModule component.
pvbus_control_s PVBus Slave This slave port provides memory-mapped read/write access to the control registers of the module.
pvbus_read_s PVBus Slave This slave port provides memory-mapped read access to a different set of registers. It is not implemented.

MemoryMappedCounterModule - parameters

This section describes the parameters.

Table 4-81 MemoryMappedCounterModule parameters

Name Type Allowed values Default value Description
non_arch_start_at_default bool true, false false A model-specific way of enabling the counter module out of reset.
base_frequency uint32_t - 100000000 Reset value for the CNTFID0 register; base frequency in Hz.
use_real_time bool true, false false Update the Generic Timer counter at a real-time base frequency instead of simulator time.
non_arch_fixed_frequency uint32_t - 0 If set, ignore CNTFID0 and instead use this frequency in Hz.
cntcidr0123_C uint32_t - 0 Values to return for control-frame CIDR registers.
cntpidr0123_C uint32_t - 0 Values to return for control-frame PIDR registers 0-3.
cntpidr4567_C uint32_t - 0 Values to return for control-frame PIDR registers 4-7.
cntcidr0123_R uint32_t - 0 Values to return for read-frame CIDR registers.
cntpidr0123_R uint32_t - 0 Values to return for read-frame PIDR registers 0-3.
cntpidr4567_R uint32_t - 0 Values to return for read-frame PIDR registers 4-7.
readonly_is_WI bool true, false false Ignore (rather than failing) on writes to read-frame.
diagnostics uint32_t 0-4 0 Diagnostics.

MemoryMappedCounterModule - verification and testing

This component passes tests as part of a system with network functionalities.

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