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4.4.37 PL022_SSP component
This section describes the PL022_SSP component.
PL022_SSP - about
This LISA+ component is a model of an ARM PL022 Synchronous Serial Port (SSP) PrimeCell.
Although the PL022_SSP component has clock input, it is not internally clock-driven. This is different to the equivalent hardware.
Note
This component is a preliminary release. It is provided as-is with the VE reference platform model, and is not a fully supported peripheral.PL022_SSP - ports
This section describes the ports.
Table 4-100 PL022_SSP ports
Name | Protocol | Type | Description |
---|---|---|---|
clk |
ClockSignal | Slave | Main PrimeCell SSP clock input |
clkin |
ClockSignal | Slave | PrimeCell SSP clock input |
pvbus |
PVBus | Slave | Slave port for connection to PV bus master/decoder |
rxd |
ValueState | Slave | PrimeCell SSP receive data |
clkout |
ClockSignal | Master | Clock output |
intr |
Signal | Master | Interrupt signaling |
rorintr |
Signal | Master | Receive overrun interrupt |
rtintr |
Signal | Master | Receive timeout interrupta |
rx_dma_port |
PL080_DMAC_DmaPortProtocol | Master | PrimeCell SSP receive DMA port |
rxintr |
Signal | Master | Receive FIFO service request port |
tx_dma_port |
PL080_DMAC_DmaPortProtocol | Master | PrimeCell SSP transmit DMA port |
txd |
ValueState | Master | PrimeCell SSP transmit data |
txintr |
Signal | Master | Transmit FIFO service request |
Related reference
PL022_SSP - registers
This section describes the registers.
Table 4-101 PL022_SSP registers
Name | Offset | Access | Description |
---|---|---|---|
SSPCR0 |
|
Read/write | Control register 0 |
SSPCR1 |
|
Read/write | Control register 1 |
SSPDR |
|
Read/write | FIFO data |
SSPSR |
|
Read only | Status |
SSPCPSR |
|
Read/write | Clock prescale |
SSPIMSC |
|
Read/write | Interrupt mask set/clear |
SSPRIS |
|
Read only | Raw interrupt status |
SSPMIS |
|
Read only | Masked interrupt status |
SSPICR |
|
Write only | Interrupt clear |
SSPDMACR |
|
Read/write | DMA control |
SSPeriphID0 |
|
Read only | Peripheral ID bits[7:0] |
SSPeriphID1 |
|
Read only | Peripheral ID bits[15:8] |
SSPeriphID2 |
|
Read only | Peripheral ID bits[23:16] |
SSPeriphID3 |
|
Read only | Peripheral ID bits[31:24] |
SSPPCellID0 |
|
Read only | PrimeCell ID bits[7:0] |
SSPPCellID01 |
|
Read only | PrimeCell ID bits[15:8] |
SSPPCellID |
|
Read only | PrimeCell ID bits[23:16] |
SSPPCellID3 |
|
Read only | PrimeCell ID bits[31:24] |
PL022_SSP - verification and testing
The functions of this component have been tested individually by using a tailored test suite. The component has not been validated against a target operating system, but improved support is expected in the next release.
a
Not supported.