This section describes the BP141_TZMA component.
BP141_TZMA - about
This LISA+ component is a model of the ARM PrimeCell Infrastructure AMBA 3 AXI TrustZone Memory Adapter (BP141).
It permits a single physical memory cell of up to 2MB to be shared between a secure and non-secure storage area. The partitioning between these areas is flexible.
This component routes transactions according to the:
- Memory region that they are attempting to access.
- Security mode of the transaction.
The BP141_TZMA fixes the base address of the secure region to the base address of the decode space. It uses the R0SIZE[9:0] input to configure the size of the secure region in 4KB increments up to a maximum of 2MB.
TZMEMSIZE is the maximum addressing range
of the memory as defined by that parameter. By default,
set to 2MB. AxADDR is the offset address that the transactions want
Table 4-30 BP141_TZMA security control
|AxADDR||Memory Region||Non-secure Transfer||Secure Transfer|
|AxADDR < R0Size||Secure, R0||Illegal||Legal|
R0SIZE <= AxADDR and AxADDR <
BP141_TZMA - ports
This section describes the ports.
Table 4-31 BP141_TZMA ports
||Value||Slave||A software interface that is driven from the TrustZone Protection Controller (TZPC), setting the secure region size by bits[9:0].|
||PVBus||Slave||Slave port for connection to PV bus master/decoder|
||PVBus||Master||Routed PVBus output|
BP141_TZMA - parameters
This section describes the parameters.
Table 4-32 BP141_TZMA parameters
|Name||Type||Allowed values||Default value||Description|
||Sets the maximum size of the addressable memory. ARM deprecates this parameter.|
||Multiples of 4096||4096||Configures the size of the region allocated for secure access for each increment of the R0Size value.|
||Configures the initial region configuration value so that an external secure control is not required.|
BP141_TZMA - verification and testing
This component passes tests separately by using its own test suite and as part of the VE example system by using VE test suites and by booting operating systems.