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PL111_CLCD component

This section describes the PL111_CLCD component.

PL111_CLCD - about

This LISA+ component is a model of the PL110 CLCD, and also implements the hardware cursor of the PL111_CLCD (ARM PrimeCell Color LCD Controller (PL111)), which is the major change compared with PL110.

PL111_CLCD - ports

This section describes the ports.

Table 4-131 PL111_CLCD ports

Name Protocol Type Description
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
intr Signal Master Interrupt signaling for flyback events
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing
display LCD Master Connection to visualization component
control Value Slave Auxiliary control register 1
pvbus_m PVBus Master DMA port for video data

PL111_CLCD - parameters

This section describes the parameters.

Table 4-132 PL111_CLCD parameters

Name Type Allowed values Default value Description
pixel_double_limit int - 300, 0x12C Threshold in horizontal pixels, below which pixels sent to the framebuffer are doubled in size horizontally and vertically.

PL111_CLCD - registers

This section describes the registers.

Table 4-133 PL111_CLCD registers

Name Offset Access Description
LCDTiming0 0x0 Read/write Horizontal timing
LCDTiming1 0x4 Read/write Vertical timing
LCDTiming2 0x8 Read/write Clock and polarity control
LCDTiming3 0xC Read/write Line end control
LCDUPBASE 0x10 Read/write Upper panel frame base address
LCDLPBASE 0x14 Read/write Lower panel frame base address
LCDControl 0x18 Read/write Control
LCDIMSC 0x1C Read/write Interrupt mask
LCDRIS 0x20 Read only Raw interrupt status
LCDMIS 0x24 Read only Masked interrupt status
LCDICR 0x28 Write only Interrupt clear
LCDIPCURR 0x2C Read only Upper panel current address
LCDLPCURR 0x30 Read only Lower panel current address
LCDPalette 0x200 - 0x3FC Read/write Palette registers
CursorImage 0x800-0xBFC Read/write Cursor image RAM register
ClcdCrsCtrl 0xC00 Read/write Cursor control
ClcdCrsrConfig 0xC04 Read/write Cursor configuration
ClcdCrsrPalette0 0xC08 Read/write Cursor palette
ClcdCrsrPalette1 0xC0C Read/write Cursor palette
ClcdCrsrXY 0XC10 Read/write Cursor XY position
ClcdCrsrClip 0xC14 Read/write Cursor clip position
ClcdCrsrIMSC 0xc20 Read/write Cursor interrupt mask set/clear
ClcdCrsrICR 0xc24 Read/write Cursor interrupt clear
ClcdCrsrRIS 0xc28 Read/write Cursor raw interrupt status
ClcdCrsrMIS 0xc2c Read/write Cursor masked interrupt status
CLCDPeriphID0 0xfe0 Read Peripheral ID register
CLCDPeriphID1 0xfe4 Read Peripheral ID register
CLCDPeriphID2 0xfe8 Read Peripheral ID register
CLCDPeriphID3 0xfec Read Peripheral ID register
CLCDPCellID0 0xff0 Read PrimeCell ID register
CLCDPCellID1 0xff4 Read PrimeCell ID register
CLCDPCellID2 0xff8 Read PrimeCell ID register
CLCDPCellID3 0xffc Read PrimeCell ID register

PL111_CLCD - verification and testing

This component passes tests as part of the PL111 test system using PL11x test suites.