PL192_VIC component
This section describes the PL192_VIC component.
PL192_VIC - about
This LISA+ component is a model of an ARM PrimeCell Vectored Interrupt Controller (PL192). It aggregates interrupts and generates interrupt signals for the ARM processor.
When coupled to an ARM processor that provides a VIC port, routing to the appropriate interrupt handler can be optionally performed in hardware, reducing interrupt latency. The PL192_VIC can also be daisy-chained with other PL192 VICs to permit more than 32 interrupts. The VIC supports hardware and software prioritization of interrupts.
PL192_VIC - ports
This section describes the ports.
Table 4-136 PL192_VIC ports
Name | Protocol | Type | Description |
---|---|---|---|
VICIntSource[ |
Signal | Slave | Interrupt source input sources |
VICVECTADDRIN |
Value | Slave | Used to receive vector address when daisy chained |
nVICFIQIN |
Signal | Slave | Used to receive FIQ signal when daisy chained |
nVICIRQIN |
Signal | Slave | Used to receive IRQ signal when daisy chained |
pvbus |
PVBus | Slave | Slave port for connection to PV bus master/decoder |
VICIRQACK |
Signal | Slave | Receive acknowledge signal from next level VIC or processor |
VICIRQACKOUT |
Signal | Master | Used to send out acknowledge signals when daisy chained |
VICVECTADDROUT |
Value | Master | Used to send vector address to next level VIC or processor |
nVICFIQ |
Signal | Master | Send out FIQ signal to the next level VIC or CPI |
nVICIRQ |
Signal | Master | Send out IRQ signal to the next level VIC or processor |
PL192_VIC - registers
This section describes the registers.
Table 4-137 PL192_VIC registers
Name | Offset | Access | Description |
---|---|---|---|
IRQSTATUS |
|
Read only | IRQ status register |
FIQSTATUS |
|
Read only | FIQ status register |
RAWINTR |
|
Read only | Raw interrupt status register |
INTSELECT |
|
Read/write | Interrupt select register |
INTENABLE |
|
Read/write | Interrupt enable register |
INTENCLEAR |
|
Write only | Interrupt enable clear register |
SOFTINT |
|
Read/write | Software interrupt register |
SOFTINTCLEAR |
|
Write only | Software interrupt clear register |
PROTECTION |
|
Read/write | Protection enable register |
SWPRIORITY |
|
Read/write | Software priority mask |
PRIORITYDAISY |
|
Read/write | Vector priority register for daisy chain |
VECTADDR[0:31] |
0x100 - |
Read/write | 32 vector addresses |
VECTPRIORITY[0:31] |
0x200 - |
Read/write | 32 priority registers |
VICADDRESS |
|
Read/write | Vector address register |
PL192_VIC - verification and testing
This component has been run against the RTL validation suite and has been successfully used in validation platforms.