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PL340_DMC component

This section describes the PL340_DMC component.

PL340_DMC - about

This LISA+ component is a model of the ARM® PrimeCell Dynamic Memory Controller (PL340).

It provides an interface for up to four DRAM chips. The implementation also provides an apb interface to configure the controller behavior.

PL340_DMC - ports

This section describes the ports.

Table 4-144 PL340_DMC ports

Name Protocol Type Description
axi_chip_if_in[4] PVBus Slave Slave bus for connecting to bus decoder
apb_interface PVBus Slave Slave bus interface for register access
axi_chip_if_out[4] PVBus Master Master to connect to DRAM

PL340_DMC - parameters

This section describes the parameters.

Table 4-145 PL340_DMC parameters

Name Type Allowed values Default value Description
IF_CHIP_0 to IF_CHIP_3 int -1, 0 -1
-1
No memory connected to the interface.
0
DRAM connected.
MEMORY_WIDTH int 16, 32, 64 32 Indicates the width, in bits, of connected memory

PL340_DMC - registers

This section describes the registers.

You can access the registers through the APB interface.

Table 4-146 PL340_DMC registers

Name Offset Access Description
memc_status 0x000 Read only Memory controller status register.
memc_cmd 0x004 Write only Modify the state machine of the controller.
direct_cmd 0x008 Write only Set the memory controller configurations.
memory_cfg 0x00C Read/write Set/read the configuration of the controller.
refresh_prd 0x010 Read/write Refresh period register
cas_latency 0x014 Read/write CAS latency register
t_dqss 0x018 Read/write t_dqss register
t_mrd 0x01C Read/write t_mrd register
t_ras 0x020 Read/write t_ras register
t_rc 0x024 Read/write t_rc register
t_rcd 0x028 Read/write t_rcd register
t_rfc 0x02C Read/write t_rfc register
t_rp 0x030 Read/write t_rp register
t_rrd 0x034 Read/write t_rrd register
t_wr 0x038 Read/write t_wr register
t_wtr 0x03C Read/write t_wtr register
t_xp 0x040 Read/write t_xp register
t_xsr 0x044 Read/write t_xsr register
t_esr 0x048 Read/write t_esr register
id_00_cfg 0x100 Read/write Set the QOS.
id_01_cfg 0x104 Read/write Set the QOS.
id_02_cfg 0x108 Read/write Set the QOS.
id_03_cfg 0x10C Read/write Set the QOS.
id_04_cfg 0x110 Read/write Set the QOS.
id_05_cfg 0x114 Read/write Set the QOS.
id_06_cfg 0x118 Read/write Set the QOS.
id_07_cfg 0x11C Read/write Set the QOS.
id_08_cfg 0x120 Read/write Set the QOS.
id_09_cfg 0x124 Read/write Set the QOS.
id_10_cfg 0x128 Read/write Set the QOS.
id_11_cfg 0x12C Read/write Set the QOS.
id_12_cfg 0x130 Read/write Set the QOS.
id_13_cfg 0x134 Read/write Set the QOS.
id_14_cfg 0x138 Read/write Set the QOS.
id_15_cfg 0x13C Read/write Set the QOS.
chip_0_cfg 0x200 Read/write Set up the external memory device configuration.
chip_1_cfg 0x204 Read/write Set up the external memory device configuration.
chip_2_cfg 0x208 Read/write Set up the external memory device configuration.
chip_3_cfg 0x20C Read/write Set up the external memory device configuration.
user_status 0x300 Read only User status register
user_config 0x304 Write only User configuration register
periph_id_0 0xFE0 Read only Peripheral ID register 0a
periph_id_1 0xFE4 Read only Peripheral ID register 1a
periph_id_2 0xFE8 Read only Peripheral ID register 2a
periph_id_3 0xFEC Read only Peripheral ID register 3a
pcell_id_0 0xFF0 Read only PrimeCell ID register 0a
pcell_id_1 0xFF4 Read only PrimeCell ID register 1a
pcell_id_2 0xFF8 Read only PrimeCell ID register 2a
pcell_id_3 0xFFC Read only PrimeCell ID register 3a

PL340_DMC - verification and testing

The PL340_DMC functions of the component have been tested individually using a tailored test suite.

a This register has no CADI interface.
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