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ARMAEMv8AMPCT component

This section describes the ARMv8-A AEMv8-A Architecture Envelope Model (AEM) component.

ARMAEMv8AMPCT - parameters

This section describes the parameters.

ARMAEMv8AMPCT cache parameters

Table 3-1 ARMAEMv8AMPCT cache parameters

Parameter Allowed values Default value Description
BPIMVA_causes_translation_lookup true, false false Performs a translation when BPIMVA is executed, that can cause both a translation table walk, or a translation fault.
cache-log2linelen 0x4-0x8 0x6 Log2(cache-line length, in bytes).
cache_maintenance_hits_watchpoints true, false false Enable AArch32 cache maintenance by DCIMVAC to trigger watchpoints.a
CTR-L1Ip-override 0-3 0 If nonzero, overrides the L1Ip bits in the CTR/CTR_EL0 system register. This parameter does not change the behavior of the cache, only what is present in the CTR register.
dcache-size 0x4000-0x100000 0x8000 L1 D-cache size, in bytes.
dcache-ways 0x1-0x40 0x2 The number of L1 D-cache ways.b
DCZID-log2-block-size 0x0-0x9 0x8 Log2(block size) cleared by DC ZVA instruction.c
icache-size 0x4000-0x100000 0x8000 L1 I-cache size, in bytes.
icache-ways 0x1-0x40 0x2 The number of L1 I-cache ways.b
l2cache-size 0x0-0x1000000 0x80000 L2 cache size, in bytes.
l2cache-ways 0x1-0x40 0x10 The number of L2 cache ways.b
memory.l2_cache.is_inner_cacheable true, false true L2 cache is inner cacheable, not outer cacheable.
memory.l2_cache.is_inner_shareable true, false true L2 cache is inner shareable, not outer shareable.
treat-dcache-invalidate-as-clean-invalidate true, false false Treats data cache invalidate operations as clean and invalidate.

ARMAEMv8AMPCT cluster parameters

Note:

The cluster identifier range is 0-1.

Table 3-2 ARMAEMv8AMPCT cluster parameters

Parameter Allowed values Default value Description
abort_execution_from_device_memory true, false false Abort on execution from device memory.
ADFSR-AIFSR-implemented true, false false Implements ADFSR and AIFSR.
advsimd_overread true, false false AdvSIMD element load operations access all bytes of a 16-byte aligned window, even in Device memory.
apsr_read_restrict true, false false At EL0, unknown bits of APSR are RAZ.
auxilliary_feature_register0

0x0-0xFFFFFFFF

0x0 Value for Auxiliary Feature Register 0 (ID_AFR0).
branch-predictor-clear-policy 0x0-0x4 0x2

Sets the branch prediction policy as defined for MMFR1[31:28]. This parameter does not change the behavior of the branch predictor, only what is reported in MMFR1.BPred.

branch-predictor-supported-ops 0x0-0x2 0x1

Sets the branch prediction policy as defined for MMFR3[11:8]. This parameter does not change the behavior of the branch predictor, only what is reported in MMFR3.BPMaint.

clear_reg_top_eret 0x0-0x2 0x1

Clears or preserves the top 32 bits of general purpose registers on exception return. 0, preserve. 1, clear to zero. 2, random choice of preserve or clear to zero.

cpacr_trcdis_behaviour 0-2 2

If there is an ETM CP14 interface, how CPACR.TRCDIS/NSACR.NSTRCDIS behaves. 0, RAZ/WI. 1, reserved. 2, implemented.

CTIPIDR 0x0-0xFFFFFFFFFF 0x0 If nonzero, override the CTI Peripheral Identification Register.
DBGBCR_BT_applies_RES0_before_valid_check true, false true If set, RES0 behavior is applied to DBGBCR(_EL1).BT before checking for reserved values for this field.
dbgitr_buffer_size 0x0-0xFFFFFFFF 0x0 Number of instructions that can be buffered before EDSCR.ITE is cleared.
DBGPIDR

0x0-0xFFFFFFFFFF

0x0 If zero, build a value for the DeBuG Peripheral Identification Register, DBGPIDR. If nonzero, override DBGPIDR with this value.
debug_rom_is_flat true, false false If true, present a debug ROM table recommended by ARMv8 Debug Architecture. Otherwise, use nested ROM tables.
delay_serror

0x0-0xFFFFFFFF

0x0 Minimum propagation delay of the System Error (SERR) signal into the cluster. Accurate in low-latency mode, -C cpu.scheduler_mode=1, but otherwise, any delay might be larger.
el0_el1_only_non_secure true, false false Controls the security state of EL0 and EL1 if neither EL2 nor EL3 are implemented. true means non-secure.
enable_tlb_contig_check true, false true Check consistency of TLB entries in regions with the Contiguous Bit set.
exception_return_treats_SPSR_J_as_0 true, false false Exception return treats SPSR.J as RAZ/WI.
exercise_stxr_fail true, false false When true, returns a pseudorandom majority of Store Exclusive Register (STXR) instructions as Failed.
ext_abort_device_read_is_sync true, false true Synchronous reporting of device read external aborts.
ext_abort_device_write_is_sync true, false false Synchronous reporting of device write external aborts.
ext_abort_fill_data - 0xFDFDFDFCFCFDFDFD Returned data, if external aborts are asynchronous.
ext_abort_normal_cacheable_read_is_sync true, false true Synchronous reporting of normal cacheable-read external aborts.
ext_abort_normal_cacheable_write_is_sync true, false false Synchronous reporting of normal cacheable write external aborts.
ext_abort_normal_noncacheable_read_is_sync true, false true Synchronous reporting of normal non-cacheable-read external aborts.
ext_abort_normal_noncacheable_write_is_sync true, false false Synchronous reporting of normal non-cacheable write external aborts.
ext_abort_prefetch_is_sync true, false true Synchronous reporting of instruction-fetch external aborts.
ext_abort_so_read_is_sync true, false true Synchronous reporting of strongly ordered read external aborts.
ext_abort_so_write_is_sync true, false true Synchronous reporting of strongly ordered write external aborts.
ext_abort_ttw_cacheable_read_is_sync true, false true Synchronous reporting of TTW cacheable read external aborts.
ext_abort_ttw_noncacheable_read_is_sync true, false true Synchronous reporting of TTW non-cacheable read external aborts.
exception_catch_type 0-2 0

Type of exception catch. 0, exception trapping. 1, non-exception trapping, higher priority than step. 2, non-exception-trapping, lower priority than step.

force_align_pc true, false false Unpredictable branch to non-word-aligned address in ARM state is forced to be aligned.
fpcr_short_vector_raz true, false false FPSCR and FPCR fields LEN and STRIDE are hardwired to 0.
has_aarch32_dbgdidr_etc true, false true DBGDIDR, DBGDRAR, DBGDSAR exist even if EL1 does not implement AArch32.
has_exception_trapping_form_of_vector_catch true, false true Implement the exception trapping form of a vector catch debug event.
has_pmu true, false true Implement the optional Performance Monitors Extension.
has_tlb_conflict_abort true, false false Inconsistent TLB content generates aborts.
has_16k_granule true, false false Implements a 16k LPAE translation granule.
has_4k_granule true, false true Implements a 4k LPAE translation granule.
has_64k_granule true, false true Implements a 64k LPAE translation granule.
has_16bit_asids true, false true Enables 16-bit Address Space IDentifiers (ASIDs).
has_delayed_sysreg true, false false Delays the functional effect of system register writes until ISB or implicit barrier.
has_el2 true, false true Enables EL2.
has_el3 true, false true Enables EL3.
has_large_system_ext true, false false

Implement the ARMv8-A Large System Extensions. This feature is at Alpha release quality.

has_hardware_translation_table_update 0x0-0x2 0x2

Perform updates to page table access flag and dirty bit if the Large System Extensions are enabled. 0, no hardware updates. 1, support bit access updates. 2, support bit access updates, and dirty bit mechanism.

has_writebuffer true, false false Implements write access buffering before L1 cache. This parameter might affect ext_abort behavior.
hcptr_tta_behaviour 0-2 2

If there is no ETM CP14 interface, how HCPTR.TTA behaves. 0, RAZ/WI. 1, RAO/WI. 2, stateful.

hcr_swio_res1 true, false false Determines whether HCR.SWIO and/or HCR_EL2.SWIO are RES1.
hsr_uncond_cc true, false false Condition codes reported in HSR as AL if it passes.
icache-log2linelen 0x4-0x8 0x0

If nonzero, log2 of the instruction cache line length in bytes (valid values in the range 4 to 8). Otherwise use cache - log2linelen.

instruction_tlb_size 0x0-0xFFFFFFFF 0x0 Number of stage 1 and stage 2 ITLB entries. 0x0 for unified ITLB + DTLB.
is_uniprocessor true, false false true for a single core implementation. When true, NUM_CORES must be 0x1.
itd_conditional_instructions_are_32bit true, false false With ITD set, an IT instruction plus a T16 instruction are considered to be a single 32-bit conditional instruction.
max_32bit_el 0x1-0x3 0x3 Maximum exception level supporting AArch32 modes. 0x1 means no support.
MIDR

0x0-0xFFFFFFFF

0x410FD0F0 Value for Main ID Register (MIDR).
mixed_endian 0x0-0x2 0x1

Enables the core to change the endianness at runtime. 0x0, not supported. 0x1, supported at all exception levels. 0x2, supported at EL0 only.

mvbar_reset_is_rvbar true, false true

If true then the reset value of MVBAR is RVBAR. If false then the rest value is unknown.

NUM_CORES 0x1-0x4 0x4 Number of cores implemented.
PA_SIZE 0x0-0x30 0x28 Physical address size, in bits.
pmu-num_counters 0x0-0x1F 0x8 Number of PMU counters implemented.
PMUPIDR 0x0-0xFFFFFFFFFF 0x0 If nonzero, override the PMU Peripheral Identification Register.
register_reset_data - 0x0 Fills data for register bits when they become unknown at reset.
report_iside_cmo_ifsr true, false true Fault information for an iside cache maintenance operation is reported in the IFSR.
scheduler_mode 0x0-0x2 0x0

Controls instruction interleaving. 0, default long quantum. 1, low latency mode, short quantum, and signal checking. 2, lock-breaking mode, long quantum with additional context switches near load-exclusive instructions.

scr_nET_writeable true, false false Whether SCR.nET is writable. Writing to it is purely cosmetic. Note: it does not implement nET behavior.
scramble_unknowns_at_reset true, false true Fills in unknown bits in registers at reset with register_reset_data.
spsr_el3_is_mapped_to_spsr_mon true, false true Defines whether SPSR_EL3 is mapped to AArch32 register SPSR_mon.
stage12_tlb_size 0x1-0xFFFFFFFF 0x80 Number of stage 1 and stage 2 TLB entries.
stage1_tlb_size 0x0-0xFFFFFFFF 0x0 Number of stage 1 TLB entries.
stage2_tlb_size 0x0-0xFFFFFFFF 0x0 Number of stage 2 TLB entries.
stage1_walkcache_size 0x0-0xFFFFFFFF 0x0 Number of stage 1 TLB walk-cache entries.
stage2_walkcache_size 0x0-0xFFFFFFFF 0x0 Number of stage 2 TLB walk-cache entries.
treat_wfi_wfe_as_nop true, false false If set, never goes into wait state for WFI or WFE instructions.
take_ccfail_undef true, false true In AArch32, take an Undefined Instruction exception even if the instruction fails its condition-codes check.
tidcp_traps_el0_undef_imp_def true, false true The TIDCP bit traps, in EL0, undefined implementation defined instructions accessing coprocessor registers.
treat_pld_as_nop true, false false If set, treat PLD as NOP.
treat_pli_as_nop true, false false If set, treat PLI as NOP.
unpredictable_exclusive_abort_memtype 0x0-0x2 0x0

MMU abort if exclusive access is not supported. 0x0, none. Exclusives are permitted in all memory. 0x1, exclusives abort in Device memory. 0x2, exclusives abort in any memory type other than WB inner cacheable.

unpredictable_hvc_behaviour 0x0-0x1 0x0

Defines HVC unpredictable behavior in HYP mode, EL2, when the SCR.HCE bit is clear. 0x0, Undefined Instruction. 0x1, NOP instruction.

unpredictable_smc_behaviour 0x0-0x1 0x0

Defines SMC unpredictable behavior in Secure mode, EL3, when the SCR.SCD bit is clear. 0x0, Undefined Instruction. 0x1, NOP instruction.

use_tlb_contig_hint true, false false Page table entries with the Contiguous Bit set generate large TLB entries.
warn_unpredictable_in_v7 true, false false Warns of unpredictable behavior in ARMv7.
watchpoint-log2secondary_restriction 0x0-0x3F 0x0 Log2(secondary restriction of FAR/EDWAR) on watchpoint hit for load and store operations.

ARMAEMv8AMPCT cache latency cluster parameters

Note:

  • These latencies are only effective when you enable cache-state modeling.
  • Timing annotation for transactions downstream of the cache models propagates through the cache models.

Table 3-3 ARMAEMv8AMPCT cache latency cluster parameters

Parameter Type Allowed values Default value Description
dcache-maintenance_latency uint32_t - 0x0 L1 D-cache timing annotation latency for cache maintenance operations, given in total ticks. For use when dcache-state_modelled=true.
dcache-read_latency uint32_t - 0x0 L1 D-cache timing annotation latency for read accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.
dcache-snoop_data_transfer_latency uint32_t - 0x0 L1 D-cache timing annotation latency for received snoop accesses that perform a data transfer. It is given in ticks per byte accessed. For use when dcache-state_modelled=true.
dcache-write_latency uint32_t - 0x0 L1 D-cache timing annotation latency for write accesses. It is given in ticks per byte accessed. For use when dcache-state_modelled=true.
icache-maintenance_latency uint32_t - 0x0 L1 I-cache timing annotation latency for cache maintenance operations, given in total ticks. For use when icache-state_modelled=true.
icache-read_latency uint32_t - 0x0 L1 I-cache timing annotation latency for read accesses given in ticks per byte accessed. For use when icache-state_modelled=true.
l2cache-maintenance_latency uint32_t - 0x0 L2 cache timing annotation latency for cache maintenance operations, given in total ticks. For use when dcache-state_modelled=true.
l2cache-read_latency uint32_t - 0x0 L2 cache timing annotation latency for read accesses given in ticks per byte accessed. For use when dcache-state_modelled=true.
l2cache-snoop_data_transfer_latency uint32_t - 0x0 L2 cache timing annotation latency for received snoop accesses that perform a data transfer. It is given in ticks per byte accessed. For use when dcache-state_modelled=true.
l2cache-snoop_issue_latency uint32_t - 0x0 L2 cache timing annotation latency for snoop accesses issued by this cache in total ticks. For use when dcache-state_modelled=true.
l2cache-write_latency uint32_t - 0x0 L2 cache timing annotation latency for write accesses. It is given in ticks per byte accessed. For use when dcache-state_modelled=true.

ARMAEMv8AMPCT core parameters

The models use the parameters for cores in sequence, from cpu0 onwards. If there are fewer cores than the maximum number, models ignore parameters for uninstantiated cores.

Note:

  • The cluster identifier range is 0-1. The core identifier range is 0-3.
  • The model needs the separate cryptography plug-in to enable the cryptographic instructions.

Table 3-4 ARMAEMv8AMPCT core parameters

Parameter Allowed values Default value Description
ase-present true, false true Enables NEON™.
CFGEND true, false false Uses big-endian order.
clock_divider 0x0-0xFFFFFFFFFF 0x1 Clock divider ratio for asymmetric MP clocking.
CONFIG64 true, false true Enables AArch64.
CP15SDISABLE true, false false Disables access to some CP15 registers in AArch32.
cpi_div - 1 Divider for calculating Cycles Per Instruction (CPI).
cpi_mul - 1 Multiplier for calculating Cycles Per Instruction (CPI).
crypto_aes 0x0-0x2 0x2

AES hash level. 0x0, AES-128. 0x1, AES-192. 0x2, AES-256.

crypto_sha1 0x0-0x1 0x1 Enable SHA1.
crypto_sha256 0x0-0x1 0x1 Enable SHA256.
CRYPTODISPOSABLE true, false false Disable cryptographic features.
cti-intack_mask 0x0-0xFF 0x1 Set bits mean that the corresponding triggers require software acknowledgment through CTIINTACK. One bit per trigger.
cti-number_of_claim_bits 0-31 0 Number of implemented bits in CTICLAIMSET.
cti-number_of_triggers 0x0-0x8 0x8 Number of CTI event triggers.
enable_crc32 true, false false Enables the optional CRC32 instruction.
etm-present true, false true Enables Embedded Trace Macrocell (ETM).
force-fpsid true, false false Overrides the FPSID value.
force-fpsid-value

0x0-0xFFFFFFFF

0x0 Value for the overridden FPSID.
has_hcptr_tase true, false true If false, HCPTR.TASE is RES0.
max_code_cache - - Maximum cache size for code translations, in bytes.
min_sync_level 0x0-0x3 0x0

Minimum CADI syncLevel. 0x0, Off. 0x1, SyncState. 0x2, PostInsnIO. 0x3, PostInsnAll.

MPIDR-override 0x0-0xFFFFFFFFFF 0x0

Overrides the MPIDR value. If this parameter is nonzero, it overrides the cluster and core ID bits in MPIDR.

number-of-breakpoints 0x2-0x10 0x10 Number of breakpoints.
number-of-context-breakpoints 0x0-0x10 0x10 Number of context-aware breakpoints.
number-of-watchpoints 0x2-0x10 0x10 Number of watchpoints.
POWERCTLI

0x0-0xFFFFFFFF

0x0 Default power control state.
RVBAR

0x0-0xFFFFFFFFFFFC

0x0 Resets the Vector Base Address when resetting into AArch64.
semihosting-ARM_SVC

0x0-0xFFFFFFFF

0x123456 A32 SVC number for semihosted calls
semihosting-cmd_line - - Program name and arguments, argc, argv, for target programs using the semihosted C library.
semihosting-cwd - - Base directory for semihosting file access.
semihosting-enable true, false true Enable semihosting of SVC instructions.d
semihosting-heap_base - 0x00000000 Virtual address of heap base.
semihosting-heap_limit - 0x0F000000 Virtual address of top of heap.
semihosting-stack_base - 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit - 0x0F000000 Virtual address of stack limit.
semihosting-stderr_istty true, false true Result of the semihost istty call when the argument is stderr.e
semihosting-stdin_istty true, false true Result of the semihost istty call when the argument is stdin.
semihosting-stdout_istty true, false true Result of the semihost istty call when the argument is stderr.e
semihosting-Thumb_SVC

0x0-0xFFFFFFFF

0xAB T32 SVC number for semihosted calls.
semihosting-use_stderr true, false false Redirects stderr output from the target program to stderr of the simulator process, rather than through CADI.e
SMPnAMP true, false true This core is in the inner shared domain, and uses its cache coherency protocol. This parameter is a model only parameter, not a synthesize option or a configuration port. In hardware, it is a design choice.
TEINIT true, false false Controls the initial state of SCTLR.TE in AArch32. When set, causes AArch32 exceptions, including reset, to be taken in T32 mode.
unpredictable_non-contigous_BAS true, false true Treat non-contiguous BAS field in the watchpoint control register as all ones.
unpredictable_WPMASKANDBAS 0-3 1

Constrained unpredictable handling of watchpoints when mask and BAS fields specified. 0, IGNOREMASK. 1, IGNOREBAS. 2, REPEATBAS8. 3, REPEATBAS.

vfp-enable_at_reset true, false false Enables coprocessor access and VFP at reset. This behavior is model-specific. It has no hardware equivalent.
vfp-present true, false true Enables floating-point arithmetic.
vfp-traps true, false true Enables hardware trapping of VFP exceptions for VFPv4U.
VINITHI true, false false Enables high vectors. The base address is 0xFFFF0000.

ARMAEMv8AMPCT TLB latency cluster parameters

Note:

  • The walk_cache_latency parameter is only available for AEMv8 clusters and is only effective when you configure the walk cache with a non-zero size.
  • Timing annotation for transactions downstream of the TLB model propagates through the TLB model.

Table 3-5 ARMAEMv8AMPCT TLB latency cluster parameters

Parameter Type Allowed values Default value Description
ptw_latency uint32_t - 0x0 Page table walker latency for Timing Annotation (TA), in simulation ticks.
tlb_latency uint32_t - 0x0 TLB latency for TA, in simulation ticks.
walk_cache_latency uint32_t - 0x0 Walk cache latency for TA, in simulation ticks.

ARMAEMv8AMPCT GIC parameters

Table 3-6 ARMAEMv8AMPCT GIC parameters

Parameter Allowed values Default value Description
dic-spi_count 0x0-0xE0 0x40 Number of Shared Peripheral Interrupts (SPIs) supported.
gic.GICC-offset 0x0-0xFF000 0x0 Offset from PERIPHBASE for GICC registers.
gic.GICD-offset 0x0-0xFF000 0x40000 Offset from PERIPHBASE for GICD registers. Ignored when the GICv3 CPU interface is enabled, because the distributor is then external to the cluster.
gic.GICH-offset 0x0-0xFF000 0x10000 Offset from PERIPHBASE for GICH registers.
gic.GICH-other-CPU-offset 0x0-0xFF000 0x40000 From PERIPHBASE for GICH registers for accessing other cores in the cluster. Set to 0 to disable.
gic.GICV-offset 0x0-0x100000 0x40000 Size of registers that are based at PERIPHBASE that are considered to be owned by the GIC. Any accesses in the range PERIPHBASE-PERIPHBASE+gic. (PERIPH - size - 1) that do not match GIC registers are treated as RAZ/WI.
gicv3.A3-affinity-supported true, false false Determines whether a nonzero value for affinity at level 3 is supported.
gicv3.BPR-min 0x0-0x3 0x2 Minimum value for GICC_BPR. The Non-secure version is this value + 1.
gicv3.cpuintf-mmap-access-level 0x0-0x2 0x0

Defines memory mapped access level. 0x0, GICC, GICH, and GICV registers. 0x1, only GICV registers. 0x2, not supported.

gicv3.EOI-check-CPUID true, false false Check CPU ID specified for accesses to EOI registers instead of ending the highest priority active interrupt.
gicv3.EOI-check-ID true, false false Check the Interrupt ID specified for accesses to EOI registers instead of ending the highest priority active interrupt.
gicv3.EOI-deactivate-any-interrupt true, false false Permit an EOI to deactivate interrupts that are not the highest priority active interrupt. EOI-ignore-out-of-order must be false otherwise this parameter is ignored.
gicv3.EOI-ignore-out-of-order true, false true Ignore EOI writes that cannot end the highest priority active interrupt.
gicv3.HCR-VARE-is-raz true, false false Virtual ARE bit in ICH_HCR_EL2 register is RAZ/WI.
gicv3.ignore-DIR-write-when-EOImode-not-set true, false true Ignore unpredictable access to the GICC_DIR register.
gicv3.IIDR_base

0x0-0xFFFFFFFF

0x43B Base value for calculating the GICC_IIDR value.
gicv3.LR-count 0x0-0x40 0x10 Number of implemented list registers.
gicv3.physical-ID-bits 0x10-0x18 0x10 Number of physical ID bits implemented.
gicv3.PMHE-RAO-WI true, false false ICC_CTLR_EL*.PHME is read as one, write ignored.
gicv3.priority-bits 0x4-0x8 0x5 Number of priority bits implemented.
gicv3.SRE-enable-action-on-mmap 0x0-0x2 0x0

Defines mmap access. 0x0, SRE one allows mmap access. 0x1, SRE one disables mmap access. 0x2, SRE one makes map access RAZ/WI.

gicv3.SRE-EL3-set-once true, false false Restrict SRE EL3 to be set only once.
gicv3.STATUSR-implemented true, false true If the GICv3 core interface is enabled, enable STATUS registers.
gicv3.VBPR-min 0x0-0x3 0x2

Minimum value for the GICV_BPR register. The Non-secure version is this value + 1.

gicv3.virtual-ID-bits 0x10-0x18 0x10 Number of virtual ID bits implemented.
gicv3.virtual-priority-bits 0x4-0x8 0x5 Number of virtual priority bits implemented.
non_secure_vgic_alias_when_ns_only

0x0-0xFFFFFFFFFFFF

0x0 If there is no EL3 and no Secure state, the VGIC has a Secure alias. If this parameter is nonzero, the model forms a Non-secure alias from its value for the VGIC, aligned to 32KB.
a Unpredictable.
b Sets are implicit from size.
c As read from DCZID_EL0.
d Semihosting is a method of running your target software on the model to communicate with the host environment. The AEM models permit the target C library to access the I/O facilities of the host computer, such as the filesystem, keyboard input, and clock.
e Semihosted programs communicate with the console by opening the file :tt. The newlib c library has introduced the convention that opening :tt in append mode represents stderr output, while opening :tt in write mode represents stdout output.
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