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ARMAEMv8MCT component

This section describes the ARMv8-M Architecture Envelope Model (AEM) processor core component.

ARMAEMv8MCT - parameters

This section describes the parameters.

Table 3-74 ARMAEMv8MCT - parameters

Parameter Type Allowed values Default value Description
architecture-version uint32_t 6-8 7 6=v6M, 7=v7M, 8=v8M.
ASP bool true, false true Include support for asset protection in the system.
baseline bool true, false true If v8-M, profile is baseline, otherwise mainline.
BB_PRESENT bool true, false false Support bit-banding.
BIGENDINIT bool true, false false Initialize core to big-endian mode.
BKPT uint32_t 0-127 8 The number of breakpoint unit comparators.
DBG bool true, false true Whether or not the debug extensions are implemented.
dcache-size uint32_t 0x0-0x100000 0x8000 L1 D-cache size in bytes.
dcache-state_modelled bool true, false true Whether L1 D-cache state is modeled.
dcache-ways uint32_t 1-64 4 L1 D-cache ways (sets are implicit from size).
DP_FLOAT bool true, false true Support 64-bit floats in VFP.
dtcm_enable bool true, false false DTCM enabled on reset.
dtcm_size uint32_t 0x0-0x4000 0x100 DTCM size in KB.
icache-size uint32_t 0x0-0x100000 0x8000 L1 I-cache size in bytes.
icache-state_modelled bool true, false true Whether L1 I-cache state is modeled.
icache-ways uint32_t 1-64 2 L1 I-cache ways (sets are implicit from size).
ID_MMFR0.Auxiliary_registers bool true, false true Auxiliary registers bits in ID_MMFR0, indicate support for Auxiliary registers.
ID_MMFR0.Outermost_shareability uint32_t 0-15 0 Outermost shareability bits in ID_MMFR0, indicate the outermost shareability domain implemented.
INITVTOR uint32_t 0x0-0xFFFFFF80 0x0 Vector table offset at reset.
IOP bool true, false false Divert D-side transactions through io_port_* ports.
IRQDIS[0-14] uint32_t - 0 -
itcm_enable bool true, false false ITCM enabled on reset.
itcm_size uint32_t 0x0-0x4000 0x100 ITCM size in KB.
late_arrival bool true, false true Enable late arrival support.
LVL_WIDTH uint32_t 0x3-0x8 0x3 Number of bits of interrupt priority.
master_id uint32_t 0x0-0xFFFFFFFF 0x0 Master ID presented in bus transactions.
min_sync_level uint32_t 0-3 0 Force minimum syncLevel. 0=off, 1=syncState, 2=postInsnIO, 3=postInsnAll.
MPU_TYPE_NS.DREGION uint32_t - 16 Number of MPU regions (Non-secure PMSA).
MPU_TYPE_S.DREGION uint32_t - 16 Number of MPU regions (Secure PMSA).
nvic_itns string - "" Each character fixes a security state target for a given external interrupt. N implies NS, S implies S, and anything else is ignored. The largest bit is first. For example, S-NN sets external interrupts 0 and 1 to non-secure, 2 remains settable by using the NVIC_ITNP register and 3 always targets secure.
NUM_IRQ uint32_t 0x0-0x1F0 0x10 Number of user interrupts.
NUM_SAU_REGION uint32_t - 16 If including asset protection in the system, the number of SAU regions. 0 = no SAU.
rd_bus_err_behave uint32_t 0-3 1 External read aborts. 0=ignored, 1=precise, 2=imprecise, 3=imprecise except SO.
scheduler_mode uint32_t 0x0-0xFFFFFFFF 0x0 Control the interleaving of instructions in this processor. 0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions.
semihosting-cmd_line string - "" Command line available to semihosting SVC calls.
semihosting-cwd string - "" Base directory for semihosting file access.
semihosting-enable bool true, false true Enable semihosting SVC traps.
semihosting-heap_base uint32_t 0x0-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit uint32_t 0x0-0xFFFFFFFF 0x10700000 Virtual address of top of heap.
semihosting-stack_base uint32_t 0x0-0xFFFFFFFF 0x10700000 Virtual address of base of descending stack.
semihosting-stack_limit uint32_t 0x0-0xFFFFFFFF 0x10800000 Virtual address of stack limit.
semihosting-Thumb_SVC uint32_t 0x0-0xFFFFFFFF 0xAB Thumb SVC number for semihosting.
SYST uint32_t 0-2 2 Include SysTick timer functionality. 0=Absent, 1=Secure only, 2=Secure and NS.
tail_chain bool true, false true Enable tail-chaining optimization.
treat_wfi_wfe_as_nop bool true, false false For the purposes of test generation only, treat WFI and WFE as NOP.
VAL_force_slow_memory bool true, false false Force all memory accesses into the slow path.
vfp-enable_at_reset bool true, false false Enable coprocessor access and VFP after reset.
vfp-present bool true, false true Set whether the model has VFP support.
VTOR_NS bool true, false true -
VTOR_S bool true, false true -
WIC bool true, false true Include support for WIC-mode deep sleep.
WPT uint32_t 0-15 4 The number of watchpoint unit comparators.
wr_bus_err_behave uint32_t 0-3 3 External write aborts. 0=ignored, 1=precise, 2=imprecise, 3=imprecise except SO.

Table 3-75 ARMAEMv8MCT parameters - DSP extension

Parameter Type Allowed values Default value Description
AIRCR.BFHFNMINS_PRIS_writable bool true, false true Is AIRCR.BFHFNMINS bit[13], formerly BFHFNMINP, and AIRCR.PRIS bit[14], formerly PRIP, writable.
AIRCR.VECTCLRACTIVE_changes_mode bool true, false true -
ID_ISAR1.extend_instrs uint32_t 0-2 2 Level of support for extend instructions, under the control of support_dsp_ext.
ID_ISAR2.multS_instrs uint32_t 0-3 3 Level of support for advanced signed multiply instructions, under the control of support_dsp_ext.
ID_ISAR2.multU_instrs uint32_t 0-2 2 Level of support for advanced unsigned multiply instructions, under the control of support_dsp_ext.
ID_ISAR3.saturate_instrs uint32_t 0-1 1 Level of support for saturate instructions, under the control of support_dsp_ext.
ID_ISAR3.SIMD_instrs uint32_t 0-3 3 Level of support for SIMD instructions, under the control of support_dsp_ext.

Table 3-76 ARMAEMv8MCT parameters - representation by the core of an external IDAU

Warning:

These parameters might be removed in a future release.
Parametera Type Allowed values Default value Description
IDAU_REGIONn.BADDR uint32_t - 0 -
IDAU_REGIONn.ENABLE bool true, false false -
IDAU_REGIONn.EXEMPT bool true, false false -
IDAU_REGIONn.LADDR uint32_t - 0 -
IDAU_REGIONn.NSC bool true, false false -
NUM_IDAU_REGION uint32_t - 0 -

ARMAEMv8MCT - ports

This section describes the ports.

Table 3-77 Ports

Name Protocol Type Description
ahbd PVBus slave Debug AHB. Core bus slave that is driven by the DAP.
ahbp_m PVBus master The core generates Vendor System data accesses on this port.
ahbs PVBus slave External master, for example DMA, can write TCMs, whether or not enabled in xTCMCR.
auxfault Value slave This is wired to the Auxiliary Fault Status Register.
bigend Signal slave Configure big-endian data format.
clk_in ClockSignal slave The clock signal that is connected to the clk_in port is used to determine the rate at which the core executes instructions.
coreconfig ValueState master Validation system only. Allow querying for the core config.
cpuwait Signal slave -
currpri Value master Current execution priority.
dap_s PVBus slave Debug Access Port (DAP).
dbgen Signal slave Invasive debug enable.
dbgrestart Signal slave External debug request.
dbgrestarted Signal master External debug request.
edbgrq Signal slave External debug request.
etm_reset Signal slave Separate reset for ETM, if parameter has_etm_reset is true.
event Signal peer This peer port of event input and output is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
fpudisable Signal slave Configure core with no FPU on reset.
fpxxc Value master Port that sends the value of the FPXXC cumulative exception flags.
halted Signal master External debug request.
initvtor_ns Value slave Reset configuration port - Non-Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset. This port remains functional whether the ARMv8-M Security Extensions are included or not. When they are not included, all exceptions use NS vector base address given by this port.
initvtor_s Value slave Reset configuration port - Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset. It becomes functional when ARMv8-M Security Extensions are included. When they are not included, this port is ignored.
intisr[496] Signal slave This signal array delivers signals to the NVIC.
intnmi Signal slave Configure non-maskable interrupt.
io_port_in PVBus slave I/O port. Used if IOP is true. Transactions from io_port_out that do not match should be returned by io_port_in.
io_port_out PVBus master I/O port. Used if IOP is true. Transactions from io_port_out that do not match should be returned by io_port_in.
locknsvtor Signal slave Disable writes to VTOR_NS.
locksvtaircr Signal slave Disable writes to VTOR_S, AIRCR.PRIS, AIRCR.BFHFNMINS.
lockup Signal master Asserted when the processor is in lockup state.
mpudisable Signal slave Configure core with no MPU on reset.
niden Signal slave Non-invasive debug enable.
poreset Signal slave Raising this signal does a power-on reset of the core.
pv_ppbus_m PVBus master The core generates External Private Peripheral Bus requests on this port.
pvbus_m PVBus master The core generates bus requests on this port.
sleepdeep Signal master Asserted when the processor is in deep sleep.
sleeping Signal master Asserted when the processor is in sleep.
spiden Signal slave Secure privileged invasive debug enable.
spniden Signal slave Secure privileged non-invasive debug enable.
stcalib Value slave The calibration value for the SysTick timer.
stclk ClockSignal slave The reference clock for the SysTick timer.
sysreset Signal slave Raising this signal puts the core into reset mode but does not reset the debug logic.
sysresetreq Signal master Asserted to indicate that a reset is required.
ticks InstructionCount master Allows the number of instructions since startup to be read from the CPU.
a Replace n with the IDAU region number, between 0 and 31.