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ARMCortexM7CT component

This C++ component is a model of an Early Access Candidate (EAC), r0p2, of a Cortex®-M7 core.

ARMCortexM7CT - ports

This section describes the ports.

Table 3-78 ARMCortexM7CT ports

Name Protocol Type Description
ahbd PVBus Slave Debug AHB: core bus slave driven by the DAP.
ahbs PVBus Slave External master (e.g. DMA) can write TCMs (whether or not enabled in xTCMCR).
auxfault Value Slave Wired to the Auxiliary Fault Status Register.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
coreconfig ValueState Master Validation system only: allow querying for the core's config.
cpuwait Signal Slave -
currpri Value Master Current execution priority.
dap_s PVBus Slave Debug Access Port (DAP).
dbgen Signal Slave Disallow (DAP) debugger access.
dbgrestart Signal Slave -
dbgrestarted Signal Master -
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
fpudisable Signal Slave Configure core with no FPU on reset.
fpxxc Value Master Port which sends the value of the FPXXC cumulative exception flags.
halted Signal Master -
intisr[240] Signal Slave This signal array delivers signals to the NVIC.
intnmi Signal Slave Configure nonmaskable interrupt.
lockup Signal Master Asserted when the processor is in lockup state.
mpudisable Signal Slave Configure core with no MPU on reset.
niden Signal Slave -
poreset Signal Slave Raising this signal power-on resets the core.
pv_ppbus_m PVBus Master The core generates External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core generates bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
stcalib Value Slave Calibration value for the SysTick timer.
stclk ClockSignal Slave Reference clock for the SysTick timer.
sysreset Signal Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.

ARMCortexM7CT - parameters

This section describes the parameters.

Table 3-79 ARMCortexM7CT parameters

Name Type Allowed values Default value Description
BIGENDINIT bool true, false false Initialize core to big-endian mode.
cpi_div uint32_t 0x1-0x7FFFFFFF 0x1 Divider for calculating CPI (Cycle Per Instruction). Runtime parameter.
cpi_mul uint32_t 0x1-0x7FFFFFFF 0x1 Multiplier for calculating CPI (Cycle Per Instruction). Runtime parameter.
DBGLVL uint32_t 0x0-0x1 0x1 0: 2 DWT, 4 FPB; 1: 4 DWT, 8 FPB comparators.
dcache-size uint32_t 0x0-0x100000 0x8000 L1 D-cache size in bytes.
dcache-state_modelled bool true, false false Set whether D-cache has stateful implementation.
dcache-ways uint32_t 1-64 4 L1 D-cache ways (sets are implicit from size).
DP_FLOAT bool true, false true Support 64-bit floats in VFP.
dtcm_enable bool true, false false DTCM enabled on reset.
dtcm_size uint32_t 0x1-0x4000 0x100 DTCM size in KB.
icache-size uint32_t 0x0-0x100000 0x8000 L1 I-cache size in bytes.
icache-state_modelled bool true, false false Set whether I-cache has stateful implementation.
icache-ways uint32_t 1-64 2 L1 I-cache ways (sets are implicit from size.
ignore_imprecise_aborts bool true, false false Suppress effects of imprecise data-aborts.
INITVTOR uint32_t 0x0-0xFFFFFF80 0x0 Vector-table offset at reset.
itcm_enable bool true, false false ITCM enabled on reset.
itcm_size uint32_t 0x1-0x4000 0x100 ITCM size in KB.
LVL_WIDTH uint32_t 0x3-0x8 0x3 Number of bits of interrupt priority.
master_id uint32_t 0x0-0xFFFFFFFF 0x0 Master ID presented in bus transactions.
min_sync_level uint32_t 0x0-0x3 0x0 Force minimum syncLevel (0 = off = default, 1 = syncState, 2 = postInsnIO, 3 = postInsnAll). Runtime parameter.
NUM_IRQ uint32_t 0x0-0xF0 0x10 Number of user interrupts.
NUM_MPU_REGION uint32_t 0-16 16 Number of MPU regions.
scheduler_mode uint32_t 0x0-0xFFFFFFFF 0x0 Control the interleaving of instructions in this processor (0 = default long quantum, 1 = low latency mode, short quantum and signal checking, 2 = lock-breaking mode, long quantum with additional context switches near load-exclusive instructions).
semihosting-cmd_line string - "" Command line available to semihosting SVC calls.
semihosting-cwd string - "" Base directory for semihosting file access.
semihosting-enable bool true, false true Enable semihosting SVN traps.
semihosting-heap_base uint32_t 0x0-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit uint32_t 0x0-0xFFFFFFFF 0x10700000 Virtual address of top of heap.
semihosting-stack_base uint32_t 0x0-0xFFFFFFFF 0x10700000 Virtual address of base of descending stack.
semihosting-stack_limit uint32_t 0x0-0xFFFFFFFF 0x10800000 Virtual address of stack limit.
semihosting-Thumb_SVC uint32_t 0x0-0xFFFFFFFF 0xAB Thumb SVC number for semihosting.
vfp-present bool true, false true Set whether model has VFP support.
WIC bool true, false true Include support for WIC-mode deep sleep.