You copied the Doc URL to your clipboard.

ARMCortexR4CT component

This section describes the ARMCortexR4CT component.

ARMCortexR4CT - about

This C++ component is a model of r1p2 of a Cortex®-R4 processor.

ARMCortexR4CT - ports

This section describes the ports.

Table 3-72 ARMCortexR4CT ports

Name Protocol Type Description
cfgiea Signal Slave Configure instruction endianness after a reset.
cfgend0 Signal Slave Initialize to BE8 endianness after a reset.
cfgnmfi Signal Slave Enable nonmaskable FIQ interrupts after a reset.
cfgte Signal Slave Initialize to take exceptions in T32 state after a reset.
clk_in ClockSignal Slave Clock input.
dtcm PVBus Slave Slave access to DTCM.
fiq Signal Slave Asynchronous FIQ signal input.
initrami Signal Slave Initialize with ITCM enabled after reset.
initramd Signal Slave Initialize with DTCM enabled after reset.
irq Signal Slave Asynchronous IRQ signal input.
itcm PVBus Slave Slave access to ITCM.
pmuirq Signal Master Performance monitoring unit IRQ output.
pvbus_m PVBus Master Master port for all memory accesses.
reset Signal Slave Asynchronous reset signal input.
standbywfi Signal Master Signal that the processor is in standby waiting for interrupts.
ticks InstructionCount Master Output that can be connected to a visualization component.
vic_ack Signal Master Acknowledge signal output for PL192 VIC.
vic_addr ValueState Slave Address input for connection to PL192 VIC. The port expects a full 32-bit address.
vinithi Signal Slave Initialize with high vectors enabled after a reset.

ARMCortexR4CT - parameters

This section describes the parameters.

Table 3-73 ARMCortexR4CT parameters

Name Type Allowed values Default value Description
CFGEND0 Boolean true, false false Initialize to BE8 endianness.
CFGIE Boolean true, false false Configure instructions as big endian.
CFGNMFI Boolean true, false false Enable nonmaskable FIQ interrupts on startup.
CFGTE Boolean true, false false Initialize to take exceptions in T32 state. Model starts in T32 state.
INITRAMD Boolean true, false false Set or reset the INITRAMD signal.
INITRAMI Boolean true, false false Set or reset the INITRAMI signal.
LOCZRAMI Boolean true, false false Set or reset the LOCZRAMI signal.
NUM_MPU_REGION Integer 0, 8, 12 8 Number of MPU regions.
VINITHI Boolean true, false false Initialize with high vectors enabled.
dcache-size Integer 4KB, 8KB, 16KB, 32KB, 64KB 0x10000 Set D-cache size in bytes.
dcache-state_modelled Boolean true, false false Set whether D-cache has stateful implementation.
dtcm0_base Integer uint32_t 0x00800000 Base address of DTCM at startup.
dtcm0_size Integer 0x0000 - 0x2000 0x8 Size of DTCM in KB.
icache-size Integer 4KB, 8KB, 16KB, 32KB, 64KB 0x10000 Set I-cache size in bytes.
icache-state_modelled Boolean true, false false Set whether I-cache has stateful implementation.
implements_vfp Boolean true, false true Set whether the model has been built with VFP support.
itcm0_base Integer uint32_t 0x00000000 Base address of ITCM at startup.
itcm0_size Integer 0x0000 - 0x2000 0x8 Size of ITCM in KB.
master_id Integer 0x0000 - 0xFFFF 0x0 Master ID presented in bus transactions
min_sync_level Integer 0-3 0 Controls the minimum syncLevel.
semihosting-ARM_SVC Integer 24-bit integer 0x123456 A32 SVC number for semihosting.
semihosting-Thumb_SVC Integer 8-bit integer 0xAB T32 SVC number for semihosting.
semihosting-cmd_lineb String No limit except memory [Empty string] Command line available to semihosting SVC calls.
semihosting-enable Boolean true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-heap_base Integer 0x00000000 - 0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit Integer 0x00000000 - 0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base Integer 0x00000000 - 0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit Integer 0x00000000 - 0xFFFFFFFF 0x0F0000000 Virtual address of stack limit.
vfp-enable_at_resetc Boolean true, false false Enable coprocessor access and VFP at reset.
cpi_mul Integer 1-0x7FFFFFFF 1 Multiplier for calculating Cycle Per Instruction (CPI).
cpi_div Integer 1-0x7FFFFFFF 1 Divider for calculating CPI.

ARMCortexR4CT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the coprocessor 14 registers and the integration and test registers.

This PV model does not model Level 1 or Level 2 caches. The system coprocessor registers related to cache operations permit cache aware software to work, but in most cases they only check register access permissions:

  • Invalidate and/or Clean Entire ICache/DCache.
  • Invalidate and/or Clean ICache/DCache by MVA.
  • Invalidate and/or Clean ICache/DCache by Index.
  • Invalidate and/or Clean Both Caches.
  • Cache Dirty Status.
  • Data Write Barrier.
  • Data Memory Barrier.
  • Prefetch ICache Line.
  • ICache/DCache lockdown.
  • ICache/DCache master valid.
  • Cache Size Override.
  • Validation registers.

ARMCortexR4CT - caches

This component implements a PV-accurate cache view.

ARMCortexR4CT - debug features

This component exports a CADI debug interface.

ARMCortexR4CT - debug - registers

All core and implemented registers are visible in the debugger.

The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior.

ARMCortexR4CT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexR4CT - debug - memory

This component presents one 4GB view of virtual memory.

ARMCortexR4CT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of uClinux on an example system.

ARMCortexR4CT - performance

This component provides high performance in all areas except with instructions in protection regions smaller than 1KB, and VFP instruction set execution.

ARMCortexR4CT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • There is a single memory port combining instruction, data, DMA and peripheral access.
  • The combined AXI slave port is not supported.
  • ECC and parity schemes are not supported (although the registers might be present).
  • The dual core redundancy configuration is not supported.
  • The hardware refers to the TCMs as "A" and "B". The model refers to these as "i" and "d".
  • The RTL permits two data TCMs, B0 and B1, to be configured for extra bandwidth. These are not modeled.
a The model implements this, although it is optional in hardware.

The value of argv[0] points to the first command line argument, not to the name of an image.


This is a model specific behavior with no hardware equivalent.