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CCI400 component

This section describes the CCI400 component.

CCI400 - about

This C++ component is a model of r1p3 of the Cache Coherent Interconnect (CCI) for AXI4.

ACE limitation

AXI Coherency Extensions (ACE) are extensions to AXI4 that support system-level cache-coherency between multiple clusters. The ACE cache models in the Cortex®-A15 and the Cortex-A7, and the ACE support in the CCI-400 have a limitation: these functional models process only one transaction at a time. Normally, the simulation processes each transaction to completion before allowing any master to generate another transaction. However, there is a situation in which the simulation might fail. Suppose a SystemC bus slave calls wait() while it is processing a transaction. This call might allow another master to issue another transaction that passes through the CCI-400 or the Cortex-A15/Cortex-A7 caches. This situation could happen if a SystemC bus master running in another thread is connected to one of the ACE-lite ports on the CCI-400.

CCI400 - ports

This section describes the ports.

Table 4-35 CCI400 ports

Name Protocol Type Description
acchannelen Value Slave For each upstream port, determine if it is enabled or not with respect to snoop requests.
barrierterminate Value Slave For each downstream port, determine if barriers are terminated at that port.
broadcastcachemain Value Slave For each downstream port, determine if broadcast cache maintenance operations are forwarded down that port.
bufferableoverride Value Slave For each downstream port, determine if all transactions are forced to non-bufferable.
errorirq Signal Master A signal stating that the imprecise error register is nonzero.
evntcntoverflow[5] Signal Master When an event counter overflows, it sets the corresponding signal.
lint_ace_3_reset_state, lint_ace_4_reset_state Signal Slave These ports can be connected to the reset signals of the system attached to the pvbus_s_ace_3 and pvbus_s_ace_4 ports.
pvbus_m PVBus Master Master port for all downstream memory accesses.
pvbus_s_ace_3, pvbus_s_ace_4 PVBus Slave ACE-capable slave ports.
pvbus_s_ace_lite_plus_dvm_0, pvbus_s_ace_lite_plus_dvm_1, pvbus_s_ace_lite_plus_dvm_2 PVBus Slave Memory bus interface that implements ACE lite and DVM protocol.
reset_in Signal Slave Signal to reset the CCI.
reset_state_of_ace_lite_ports[3] Signal Slave This port can be connected to the reset signals of the system that are attached to ACE-Lite ports 0, 1, and 2.

CCI400 - parameters

This section describes the parameters.

Table 4-36 CCI400 parameters

Name Type Allowed values Default value Description
acchannelen int 0x0-0x31 0x31 For each upstream port, determine if it is enabled or not with respect to snoop requests.
barrierterminate int 0x0-0x7 0x7 For each downstream port, determine if barriers are terminated at that port.
broadcastcachemain int 0x0-0x7 0x0 For each downstream port, a bit determines if broadcast cache maintenance operations are forwarded down that port.
bufferableoverride int 0x0-0x7 0x0 For each downstream port, determine if all transactions are forced to non-bufferable.
cache_state_modelled bool true, false true Model the cache coherency operations. Enable to correctly maintain coherency between ACE masters that model cache state.
force_on_from_start bool true, false false The CCI normally starts up with snooping disabled. However, using this permits the model to start up as enabled without having to program it. This is only set up at simulation reset and not at signal reset.
log_enabled int 0x0, 0x1, 0x2, 0x3 0x1

Enable log messages from the CCI register file:

0
Print nothing.
1
Print access violations.
2
Also print writes.
3
Also print reads.
periphbase int - 0x2C000000 Value for PERIPHBASE, using only bits [39:16]. You can override it with an input on the periphbase port.
revision string ‘r0p0’ ‘r0p0’ The revision of the component, reflected in the ID register value.

CCI400 - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies.

CCI400 - debug features

This component exports a CADI debug interface.

CCI400 - verification and testing

This component passes tests by running a switching hypervisor on an example system containing an ARMCortexA7xnCT component and an ARMCortexA15xnCT CCI400 component.

CCI400 - performance

If you disable cache_state_modelled, this component has negligible performance impact. If you enable cache_state_modelled, it adds significant cost to throughput for coherent transactions.

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