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DMC_500 component

This section describes the DMC_500 component.

DMC_500 - about

This LISA+ component is a model of the ARM® CoreLink™ DMC-500 Dynamic Memory Controller.

A platform can have multiple instances of this component. For example:

        //LISA instantiation
        composition
        {
            // Memory controllers
            dmc0                : DMC500("default_region_attributes"=dmc_default_region_attributes,
                                         "default_region_id_access"=dmc_default_region_id_access,
                                         "passthrough_debug_access"=true);
            dmc1                : DMC500("default_region_attributes"=dmc_default_region_attributes,
                                         "default_region_id_access"=dmc_default_region_id_access,
                                         "passthrough_debug_access"=true);
        }

Limitations:

  • The model does not support address striping.
  • It works with linear addresses and not in rank,bank,row,column form.
  • It does not include any mechanism for error injection or detection.
  • Scrubbing functionality is only provided from the interface point of view.
  • It does not implement direct read or write commands.
  • It does not implement any performance counters.

Interface differences:

  • All OR'd interrupt signals are missing from this release of the model. Users can connect the failed access interrupt as a substitute.
  • The model combines separate failed access interrupts for system interfaces 1 and 2 into a single failed access interrupt.
  • DMC-500 has three separate reset signals whereas this model has a single reset signal which supports the combined assertion of three resets. This model does not support separate reset signals.

DMC_500 - ports

This section describes the ports.

Table 4-54 DMC_500 - ports

Name Protocol Type Description
apb_pvbus_s PVBus slave Slave port for configuring register accesses.
failed_access_interrupt_signal Signal master The DMC has detected a system request that has failed a permissions check and a previously detected assertion was not cleared.
filter_pvbus_m PVBus master Memory transaction output to filter unit.
filter_pvbus_s PVBus slave Memory transaction input from filter unit.
reset_signal Signal slave Reset signal input.
si1_filter_pvbus_m PVBus master Output to a second independent transaction filtering unit.
si1_filter_pvbus_s PVBus slave Input from a second independent transaction filtering unit.

DMC_500 - parameters

This section describes the parameters.

Table 4-55 DMC_500 - parameters

Name Type Allowed values Default value Description
passthrough_debug_access bool true or false false Always allow debug access to memory.
default_region_attributes uint32_t 0x0-0xFFFFFFFF 0x1 Default Region Secure attributes. Bits[31:30] set secure RD/WR enable.
default_region_id_access uint32_t 0x0-0xFFFFFFFF 0x0 Default Region Non-secure access ID (NSAID) permissions. Bits[31:16] set non-secure WR enable and bits[15:0] set non-secure RD enable.

DMC_500 - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies.

DMC_500 - trace sources

This section describes the trace sources for the DMC-500 model.

DMC_AccessInResetState
DMC Register access in reset state.
DMC_AccessToUnimplementedRegister

Fields:

ADDR unsigned int
Address of the accessed register.
READ bool
Transaction type is read or write.
DMC_BlockingTransactions

Fields:

ADDR unsigned int
Address for the transaction.
MASTER_ID unsigned int
Which master initiated the transaction.
NS bool
Whether the transaction is secure or non-secure.
READ bool
Transaction type is read or write.
DMC_CheckPermissions

Fields:

ADDR unsigned int
Transaction address.
MASTER_ID unsigned int
Which master initiated the transaction.
NS bool
Whether the transaction is secure or non-secure.
OUTSIDE_DEFAULT bool
Whether the access failed due to outside default region.
READ bool
Transaction type is read or write.
SUCCESS bool
Whether transaction succeeded or failed.
TZ_FAIL bool
Whether the access failed due to invalid permissions.
DMC_ReadToWriteOnlyRegister

Fields:

ADDR unsigned int
Address of the accessed register.
DMC_RegRead

Fields:

REG_NAME string
The name of the register read.
REG_OFFSET unsigned int
The address of the register read.
VALUE unsigned int
Read Value from the register.
DMC_RegWrite

Fields:

REG_NAME string
The name of the register updated.
REG_OFFSET unsigned int
The address of the register updated.
UPDATED_VALUE unsigned int
New Value in the register.
VALUE unsigned int
Old Value in the register.
DMC_WriteToReadOnlyRegister

Fields:

ADDR unsigned int
Address of the accessed register.

DMC_500 - verification and testing

DMC-500 has been extensively used as part of the FVPs that are used for system-level testing of ARM subsystems.

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