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PL080_DMAC component

This section describes the PL080_DMAC component.

PL080_DMAC - about

This LISA+ component is a model of the ARM PL080 DMA Controller.

It provides eight configurable DMA channels, and 16 DMA ports for handshaking with peripherals. You can configure each channel to operate in one of eight flow control modes either under DMA control or the control of the source or destination peripheral. Transfers can occur on either master channel and can optionally be endian converted on both source and destination transfers.

PL080_DMAC - ports

This section describes the ports.

Table 4-127 PL080_DMAC ports

Name Protocol Type Description
pvbus_s PVBus Slave Slave bus for register accesses
clk_in ClockSignal Slave Clock signal to control DMA transfer rate
reset_in Signal Slave Reset signal
pvbus0_m PVBus Master Master bus interface 0 for DMA transfers
pvbus1_m PVBus Master Master bus interface 1 for DMA transfers
interr Signal Master DMA error interrupt signal
inttc Signal Master DMA terminal count signal
intr Signal Master Combined DMA error and terminal count signal
dma_port[16] PL080_DMAC_DmaPortProtocol Slave Peripheral handshake ports

PL080_DMAC - parameters

This section describes the parameters.

Table 4-128 PL080_DMAC parameters

Name Type Allowed values Default value Description
fifo_size Integer 0-1024 16 Controls the size of channel FIFOs in bytes
max_transfer Integer 1-1024 256 Limits the number of transfers that can be made atomically
generate_clear Boolean true, false false Controls whether completion of a burst/single transfer generates a clear response to peripherals
activate_delay Integer 0-256 0 Sets the minimum number of cycles after a request or channel enable

PL080_DMAC - registers

This section describes the registers.

Table 4-129 PL080_DMAC registers

Name Offset Access Description
IrqStatus 0x000 Read only Combined interrupt status
IrqTCStatus 0x004 Read only Masked terminal count status
IrqTCClear 0x008 Write only Terminal count clear
IrqErrStatus 0x00C Read only Masked error status
IrqErrClear 0x010 Write only Error clear
RawIrqTCStatus 0x014 Read only Raw terminal count status
RawIrqErrStatus 0x018 Read only Raw error status
EnabledChannels 0x01C Read only Enabled channels
SoftBReq 0x020 Read/write Soft burst request/status
SoftSReq 0x024 Read/write Soft single request/status
SoftLBReq 0x028 Read/write Soft last burst request/status
SoftLSReq 0x02C Read/write Soft last single request/status
Configuration 0x030 Read/write Master configuration
Sync 0x034 Read/write Synchronization control
C0SrcAddr 0x100 Read/write Channel source address
C0DstAddr 0x104 Read/write Channel destination address
C0LLI 0x108 Read/write Channel linked list item
C0Control 0x10C Read/write Channel control
C0Config 0x110 Read/write Channel configuration
C1SrcAddr 0x120 Read/write Channel source address
C1DstAddr 0x124 Read/write Channel destination address
C1LLI 0x128 Read/write Channel linked list item
C1Control 0x12C Read/write Channel control
C1Config 0x130 Read/write Channel configuration
C2SrcAddr 0x140 Read/write Channel source address
C2DstAddr 0x144 Read/write Channel destination address
C2LLI 0x148 Read/write Channel linked list item
C2Control 0x14C Read/write Channel control
C2Config 0x150 Read/write Channel configuration
C3SrcAddr 0x160 Read/write Channel source address
C3DstAddr 0x164 Read/write Channel destination address
C3LLI 0x168 Read/write Channel linked list item
C3Control 0x16C Read/write Channel control
C3Config 0x170 Read/write Channel configuration
C4SrcAddr 0x180 Read/write Channel source address
C4DstAddr 0x184 Read/write Channel destination address
C4LLI 0x188 Read/write Channel linked list item
C4Control 0x18C Read/write Channel control
C4Config 0x190 Read/write Channel configuration
C5SrcAddr 0x1A0 Read/write Channel source address
C5DstAddr 0x1A4 Read/write Channel destination address
C5LLI 0x1A8 Read/write Channel linked list item
C5Control 0x1AC Read/write Channel control
C5Config 0x1B0 Read/write Channel configuration
C6SrcAddr 0x1C0 Read/write Channel source address
C6DstAddr 0x1C4 Read/write Channel destination address
C6LLI 0x1C8 Read/write Channel linked list item
C6Control 0x1CC Read/write Channel control
C6Config 0x1D0 Read/write Channel configuration
C7SrcAddr 0x1E0 Read/write Channel source address
C7DstAddr 0x1E4 Read/write Channel destination address
C7LLI 0x1E8 Read/write Channel linked list item
C7Control 0x1EC Read/write Channel control
C7Config 0x1F0 Read/write Channel configuration
PeriphID0 0xFE0 Read only PrimeCell peripheral ID
PeriphID1 0xFE4 Read only PrimeCell peripheral ID
PeriphID2 0xFE8 Read only PrimeCell peripheral ID
PeriphID3 0xFEC Read only PrimeCell peripheral ID
PCellID0 0xFF0 Read only PrimeCell ID
PCellID1 0xFF4 Read only PrimeCell ID
PCellID2 0xFF8 Read only PrimeCell ID
PCellID3 0xFFC Read only PrimeCell ID

PL080_DMAC - verification and testing

The functions of this component have been tested individually using a tailored test suite.

PL080_DMAC - performance

This component might have a significant impact on system performance in certain flow control modes.

Channels configured for small bursts, or using single bursts, and with peripheral DMA handshaking could add significant overheads. The peripheral has not been fully optimized to make use of the advanced features of the PVBus model.