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PL110_CLCD component

This section describes the PL110_CLCD component.

PL110_CLCD - about

This LISA+ component is a model of the PL110 Color LCD (CLCD) controller PrimeCell.

You can connect the model through a framebuffer port to, for instance, a visualization component, so that LCD output can be viewed.

The implementation provides a register model of the LCD controller, and both timing and bus utilization models favor efficiency of implementation and model speed rather than accuracy.

PL110_CLCD - ports

This section describes the ports.

Table 4-130 PL110_CLCD ports

Name Protocol Type Description
pvbus PVBus Slave Slave port for connection to PV bus master/decoder
intr Signal Master Interrupt signaling for flyback events
clk_in ClockSignal Slave Master clock input, typically 24MHz, to drive pixel clock timing
display LCD Master Connection to visualization component
control Value Slave Auxiliary control register 1
pvbus_m PVBus Master DMA port for video data

PL110_CLCD - parameters

This section describes the parameters.

Table 4-131 PL110_CLCD parameters

Name Type Allowed values Default value Description
pixel_double_limit Integer - 300 Sets a threshold in horizontal pixels, below which pixels sent to the framebuffer are doubled in size horizontally and vertically

PL110_CLCD - registers

This section describes the registers.

Table 4-132 PL110_CLCD registers

Name Offset Access Description
LCDTiming0 0x000 Read/write Horizontal timing
LCDTiming1 0x004 Read/write Vertical timing
LCDTiming2 0x008 Read/write Clock and polarity control
LCDTiming3 0x00C Read/write Line end control
LCDUPBASE 0x010 Read/write Upper panel frame base address
LCDLPBASE 0x014 Read/write Lower panel frame base address
LCDIMSC 0x018 Read/write Interrupt mask
LCDControl 0x01C Read/write Control
LCDRIS 0x020 Read only Raw interrupt status
LCDMIS 0x024 Read only Masked interrupt status
LCDICR 0x028 Write only Interrupt clear
LCDIPCURR 0x02C Read only Upper panel current address
LCDLPCURR 0x030 Read only Lower panel current address
LCDPalette 0x200-0x400 Read/write Palette registers
LCDPeriphID0 0xfe0 Read Peripheral ID register
LCDPeriphID1 0xfe4 Read Peripheral ID register
LCDPeriphID2 0xfe8 Read Peripheral ID register
LCDPeriphID3 0xfec Read Peripheral ID register
LCDPCellID0 0xff0 Read PrimeCell ID register
LCDPCellID1 0xff4 Read PrimeCell ID register
LCDPCellID2 0xff8 Read PrimeCell ID register
LCDPCellID3 0xffc Read PrimeCell ID register

PL110_CLCD - verification and testing

This component passes tests as part of the VE example system by using VE test suites and by booting operating systems.

PL110_CLCD - performance

This component might affect the performance of a PV system.

The implementation is optimized for situations where the majority of the framebuffer does not change. For instance, displaying full screen video results in significantly reduced performance. Rendering pixel data into an appropriate form for the framebuffer port (rasterization) can also take a significant amount of simulation time. If the pixel data are coming from a PVBusSlave region that has been configured as memory-like, rasterization only occurs in regions where memory contents are modified.