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SP805_Watchdog component

This section describes the SP805_Watchdog component.

SP805_Watchdog - about

This LISA+ component is a model of the ARM Watchdog Module (SP805).

SP805_Watchdog - ports

This section describes the ports.

Table 4-174 SP805_Watchdog ports

Name Protocol Type Description
pvbus_s PVBus Slave Slave port for connection to PV bus master/decoder
irq_out Signal Master Interrupt signaling
reset_out Signal Master Reset signaling
clk_in ClockSignal Slave Clock input, typically 1MHz, driving master count rate
reset_in Signal Master Master reset signal

SP805_Watchdog - parameters

This section describes the parameters.

Table 4-175 SP805_Watchdog parameters

Name Type Allowed values Default value Description
simhalt bool true, false false If true, halt simulation instead of signaling reset.

SP805_Watchdog - registers

This section describes the registers.

Table 4-176 SP805_Watchdog registers

Name Offset Access Description
SP805_WDOG_Load 0x000 Read/write Load register
SP805_WDOG_VALUE 0x004 Read only Value register
SP805_WDOG_CONTROL 0x008 Read/write Control register
SP805_WDOG_INT_CLR 0x00C Write only Clear interrupt register
SP805_WDOG_RAW_INT_STATUS 0x00C Read only Raw interrupt status register
SP805_WDOG_MASKED_INT_STATUS 0x010 Read only Masked interrupt status register
SP805_WDOG_LOCK 0xC00 Read/write Register access lock register

SP805_Watchdog - verification and testing

This component passes tests as part of an integrated platform.