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DP500x2 component

This section describes the DP500x2 component.

DP500x2 - about

This component is a model of the dual display configuration of the DP500 Display Processor, with basic support for the display and scaling engines. Connect it to a visualization component to view LCD output.

It is a C++ component with a LISA wrapper.

It passes tests as part of a booting Android kernel and running under the control of the official DP500 drivers.


  • All RGB and YUV format parsing.
  • Color adjustment in Display Engine (DE).
  • Nearest neighbor scaling.
  • All layers.
  • Alpha blending.
  • Memory writeback.
  • Inverse gamma adjustment.
  • Basic layer (overlay) and register security semantics.


  • No support for polyphase scaling algorithm. Falls back to nearest neighbor when configured to do so.
  • No support for 3D or interlaced video.
  • No support for image enhancing functionality.
  • No colorspace conversion support.
  • No support for two plane YUV memory writeback.

DP500x2 - ports

This section describes the ports.

Table 4-62 DP500x2 ports

Name Protocol Type Description
dc_de_interrupt Signal Master Interrupt signalling from display engines.
dc_pvbus_m PVBus Master Bus for processors 0 and 1.
dc_se_interrupt Signal Master Interrupt signalling from scaling engines.
display LCD Master Connection to visualization component.
dp0_clk_in ClockSignal Slave Clock signal for DP0.
dp1_clk_in ClockSignal Slave Clock signal for DP1.
pvbus_s PVBus Slave Slave port for register access.
reset_signal Signal Slave Reset signal.

DP500x2 - parameters

This section describes the parameters.

Table 4-63 DP500x2 parameters

Name Type Allowed values Default value Description
disable_snooping_dma bool true, false false Disable DMA snooping.
force_frame_rate int 0-60 0 If 0, the input clock is used as PXLCLOCK. If >0, the model ensures the screen display is refreshed n times per simulated second.

DP500x2 - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies.