This section describes the PL310_L2CC component.
PL310_L2CC - about
This LISA+ component is a model of an ARM® PrimeCell Level 2 Cache Controller (PL310).
The presence of additional on-chip secondary cache can improve performance when significant memory traffic is generated by the processor. A secondary cache assumes the existence of a Level 1, or primary, cache that is closely coupled or internal to the processor.
This component has two modes of operation:
- Register view: cache control registers are present but the cache behavior is not modeled.
- Functional model: cache behavior is modeled.
cache-state_modelled parameter controls
the mode of operation.
ARM supports the use of the PL310 when connected to the ARM Cortex-A5 or Cortex-A9 processor.
PL310_L2CC - ports
This section describes the ports.
Table 4-142 PL310_L2CC ports
||PVBus||Slave||Slave port for connection to PV bus master/decoder|
||PVBus||Master||Master port for connection to PV bus master/decoder|
||Signal||Master||Decode error received on master port from L3|
||Signal||Master||Event counter overflow / increment|
||Signal||Master||Error on L2 data RAM read|
||Signal||Master||Error on L2 tag RAM read|
||Signal||Master||Error on L2 data RAM write|
||Signal||Master||Error on L2 tag RAM write|
||Signal||Master||Combined interrupt output|
||Signal||Master||Parity error on L2 data RAM read|
||Signal||Master||Parity error on L2 tag RAM read|
||Signal||Master||Slave error on master port from L3|
PL310_L2CC - parameters
This section describes the parameters.
Table 4-143 PL310_L2CC parameters
|Name||Type||Allowed values||Default value||Description|
||Associativity for auxiliary control register.|
||Cache controller cache ID.|
||Specifies whether real cache state is modeled (vs. register model).|
||Big-endian mode for accessing configuration registers out of reset.|
||Cost to handle a cache hit.|
||Cost to handle a cache miss.|
||Cost to handle one beat of cache data movement.|
||Lockdown by line.|
||Lockdown by master.|
||Base address for accessing configuration registers.|
||Size of ways for auxiliary control register.|
PL310_L2CC - registers
This section describes the registers.
Table 4-144 PL310_L2CC registers
||Read only||r0 cache ID|
||Read only||r0 cache type|
||Read/write||r1 auxiliary control|
||Read/write||r1 tag RAM latency control|
||Write only||r1 data RAM latency control|
||Read/write||r2 event counter control|
||Write only||r2 event counter 1 configuration|
||Read/write||r2 event counter0 configuration|
||Read/write||r2 event counter 1 value|
||Read/write||r2 event counter 0 value|
||Read/write||r2 interrupt mask|
||Read only||r2 masked interrupt status|
||Read only||r2 raw interrupt status|
||Write only||r2 interrupt clear|
||Read/write||r7 cache sync|
||Read/write||r7 invalidate line by PA|
||Read/write||r7 invalidate by way|
||Read/write||r7 clean line by PA|
||Read/write||r7 clean line by index or way|
||Read/write||r7 clean by way|
||Read/write||r7 clean and invalidate line by PA|
||Read/write||r7 clean and invalidate line by index or way|
||Read/write||r7 clean and invalidate by way|
||Read/write||r9 data lockdown 0 by way|
||Read/write||r9 instruction lockdown 0 by way|
||Read/write||r9 data lockdown 1 by way|
||Read/write||r9 instruction lockdown 1 by way|
||Read/write||r9 data lockdown 2 by way|
||Read/write||r9 instruction lockdown 2 by way|
||Read/write||r9 data lockdown 3 by way|
||Read/write||r9 instruction lockdown 3 by way|
||Read/write||r9 data lockdown 4 by way|
||Read/write||r9 instruction lockdown 4 by way|
||Read/write||r9 data lockdown 5 by way|
||Read/write||r9 instruction lockdown 5 by way|
||Read/write||r9 data lockdown 6 by way|
||Read/write||r9 instruction lockdown 6 by way|
||Read/write||r9 data lockdown 7 by way|
||Read/write||r9 instruction lockdown 7 by way|
||Read/write||r9 lockdown by line enable|
||Read/write||r9 unlock all lines by way|
||Read/write||r12 address filtering start|
||Read/write||r12 address filtering end|
||Read/write||r15 debug control register|
PL310_L2CC - debug features
This component exports the PL310 registers by CADI.
PL310_L2CC - verification and testing
This component has been run against the RTL validation suite and passes for supported features. It has also been tested with operating system booting in both normal and exclusive modes, and has successfully been used in validation platforms.
PL310_L2CC - performance
The performance of this component depends on the configuration of the associated L1 caches and the mode it is in.
- Register mode: no significant affect.
- Functional mode with functional-mode L1: the addition of a functional L2 cache has minimal further impact on performance when running applications that are cache-bound.
- Functional mode with a register-mode L1: there is a significant impact on system performance.
PL310_L2CC - functionality
This component implements the programmer visible functionality of the PL310, and excludes some non-programmer visible features.
PL310_L2CC - hardware features present
This component reproduces many features of the hardware.
- Physically addressed and physically tagged.
- Lockdown format C supported, for data and instructions. Lockdown format C is also known as way locking.
- Lockdown by line supported.
- Lockdown by master ID supported.
- Direct mapped to 16-way associativity, depending on the configuration and the use of lockdown registers. The associativity is configurable as 8 or 16.
- L2 cache available size can be 16KB to 8MB, depending on configuration and the use of the lockdown registers.
- Fixed line length of 32 bytes (eight words or 256 bits).
- Supports all of the AXI cache modes:
- write-through and write-back.
- read allocate, write allocate, read and write allocate.
- Force write allocate option to always have cacheable writes allocated to L2 cache, for processors not supporting this mode.
- Normal memory non-cacheable shared reads are treated as cacheable non-allocatable. Normal memory non-cacheable shared writes are treated as cacheable write-through no write-allocate. There is an option, Shared Override, to override this behavior.
- TrustZone support, with the following features:
- Non-Secure (NS) tag bit added in tag RAM and used for lookup in the same way as an address bit.
- NS bit in Tag RAM used to determine security level of evictions to L3.
- Restrictions for NS accesses for control, configuration, and maintenance registers to restrict access to secure data.
- Pseudo-Random victim selection policy. You can make this deterministic with use of lockdown registers.
- Software option to enable exclusive cache configuration.
- Configuration registers accessible using address decoding in the component.
- Interrupt triggering in case of an error response when accessing L3.
- Maintenance operations.
- Prefetching capability.
PL310_L2CC - hardware features absent
This component does not model some features of the hardware. Most of them are not relevant from a PV modeling point of view.
- There is no interface to the data and tag RAM as they are embedded to the model.
- Critical word first linefill not supported, as this is not relevant for PV modeling.
- Buffers are not modeled.
- Outstanding accesses on slave and master ports cannot occur by design in a PV model as all transactions are atomic.
- Option to select one or two master ports and option to select one or two slave ports is not supported. Only one master port and one slave port is supported.
- Clock management and power modes are not supported, as they is not relevant for PV modeling.
- Wait, latency, clock enable, parity, and error support for data and tag RAMs not included, as this is not relevant for PV modeling, and the data and tag RAMs embedded in the model cannot generate error responses.
- MBIST support is not included.
- Debug mode and debug registers are not supported.
- Test mode and scan chains are not supported.
- L2 cache event monitoring is not supported.
- Address filtering in the master ports is not supported.
- Performance counters are not supported.
- Specific Cortex-A9 related optimizations are not supported: Prefetch hints, Full line of zero and Early write response.
- Hazard detection is not required because of the atomic nature of the accesses at PV modeling and the fact that buffers are not modeled, thus hazards cannot occur.
Registers belonging to features not implemented are accessible but do not have a functionality.
PL310_L2CC - hardware features different
This component handles some features differently to the hardware.
- Error handling. DECERR from the master port is mapped to SLVERR. Internal errors in cache RAM (like parity errors) cannot happen in the model.
- Background cache operations do not occur in the background. They occur atomically.
- The LOCKDOWN_BY_LINE and LOCKDOWN_BY_MASTER parameter values are reflected in the CacheType register, but the feature is not switched off when the parameter is 0.
One feature is additional.
- Data RAM and Tag RAM are embedded to the model.
Value is reflected in CacheType register bit 25, but the feature is not switched off when the parameter is 0.
Value is reflected in CacheType register bit 26, but the feature is not switched off when the parameter is 0.