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PVBusSlave component

This section describes the PVBusSlave component.

PVBusSlave - about

This component handles decoding the slave side of the PVBus.

Any component that acts as a bus slave must:

  • Provide a PVBus slave port.
  • Instantiate a PVBusSlave subcomponent, with the size parameter configured for the address range covered by the device.
  • Connect the slave port to the pvbus_s port on the PVBusSlave.

By default, the PVBusSlave translates all transactions into read() and write() requests on the device port.

The control port enables you to configure the PVBusSlave for a device. This lets you define the behavior of the different regions of the address space on the device. You can configure regions separately for read and write, at a 4k byte granularity. This permits you to set memory-like, device-like, abort or ignore access address regions.

Transactions to memory-like regions are handled internally by the PVBusSlave subcomponent. Abort and ignore regions are also handled by the PVBusSlave.

Transactions to device-like regions are forwarded to the device port. Your device must implement the read() and write() methods on the device port if any regions are configured as device-like.

This is a C++ component.

PVBusSlave - ports

This section describes the ports.

Table 4-204 PVBus ports

Name Protocol Type Description



Handles incoming requests from bus masters.




Passes on requests for peripheral register accesses to permit the owning component to handle the request.




Enables the owning component to control which regions of the device memory are to be handled as RAM/ROM/Device. These settings can be changed dynamically. For example, when a Flash component is being programmed, it can switch to treating reads as Device requests instead of ROM requests.

pv::accessMode values

The values assigned to pv::accessMode control what happens when an address is accessed.

Legal values for the enumeration are:

Act as memory. The PVBusSlave manages the underlying storage to provide 4KB of memory, which can be ROM or RAM, depending on how you configure it to handle bus write transactions.
Act as a device. Requests to the select pages are routed to the PVBusSlave device port, where the necessary behavior can be implemented by the component.
Generate bus abort signals for any accesses to this page.
Ignore accesses to this page. Bus read requests return 0.

PVBusSlave - parameters

This section describes the parameters.

Table 4-205 PVBusSlave parameters

Name Type Allowed values Default value Description
max_access_width uin32_t Power of 2: 1, 2, 4, 8, 16 8 Maximum width of an access in bytes
size uint64_t 0 to 264 - 1, where 0 represents 264 bytes, but must also be a multiple of 0x1000 (4KB) 0 (264) Addressable size of the device in bytes

PVBusSlave - verification and testing

This component passes tests as part of the VE example system by using VE test suites and by booting operating systems.

PVBusSlave - performance

This component, typically, does not significantly affect the performance of a PV system. However, correct implementation of the PVBusSlave component is critical to the performance of the overall PV system.

For example, routing a request to a PVDevice port is slower than letting the PVBusSlave component handle the request internally. ARM recommends using the internal support for memory-like regions where possible.

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