You copied the Doc URL to your clipboard.

ARMCortexA8CT component

This section describes the ARMCortexA8CT component.

ARMCortexA8CT - about

This C++ component is a model of r2p1 of the Cortex®-A8 processor.

ARMCortexA8CT - ports

This section describes the ports.

Table 3-45 ARMCortexA8CT ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock input
pvbus_m PVBus Master Master port for all memory accesses
reset Signal Slave Asynchronous reset signal input
irq Signal Slave Asynchronous IRQ signal input
fiq Signal Slave Asynchronous FIQ signal input
pmuirq Signal Master Performance monitoring unit IRQ output
dmairq Signal Master Normal PreLoad Engine (PLE) interrupt output
dmasirq Signal Master Secure PLE interrupt output
dmaexterrirq Signal Master PLE error interrupt output
ticks InstructionCount Master Output that can be connected to a visualization component
cfgend0 Signal Slave Initialize to BE8 endianness after a reset
cfgnmfi Signal Slave Enable nonmaskable FIQ interrupts after a reset
cfgte Signal Slave Initialize to take exceptions in T32 state after a reset
vinithi Signal Slave Initialize with high vectors enabled after a reset

ARMCortexA8CT - parameters

This section describes the parameters.

Table 3-46 ARMCortexA8CT parameters

Name Type Allowed values Default value Description
CFGEND0 Boolean true, false false Initialize to BE8 endianness.
CFGNMFI Boolean true, false false Enable nonmaskable FIQ interrupts on startup.
CFGTE Boolean true, false false Initialize to take exceptions in T32 state. Model starts in T32 state.
CP15SDISABLE Boolean true, false false Initialize to disable access to some CP15 registers.
cpi_div Integer 1-0x7FFFFFFF 1 Divider for calculating Cycles Per Instruction (CPI).
cpi_mul Integer 1-0x7FFFFFFF 1 Multiplier for calculating CPI.
l1_dcache-state_modelleda Boolean true, false false Include Level 1 data cache state model.
l1_icache-state_modelleda Boolean true, false false Include Level 1 instruction cache state model.
l2_cache-state_modelleda Boolean true, false false Include unified Level 2 cache state model.
l1_dcache-size Integer 16KB, 32KB 0x8000 Set L1 D-cache size in bytes.
l1_icache-size Integer 16KB, 32KB 0x8000 Set L1 I-cache size in bytes.
l2_cache-size Integer 128KB-1024KB 0x40000 Set L2 cache size in bytes.
device-accurate-tlb Boolean true, false falseb Specify whether all TLBs are modeled.
implements_vfp Boolean true, false true Set whether the model has been built with VFP and NEON™ support.
master_id Integer 0x0000-0xFFFF 0x0 master ID presented in bus transactions
min_sync_level Integer 0-3 0 Controls the minimum syncLevel.
semihosting-ARM_SVC Integer uint24_t 0x123456 A32 SVC number for semihosting.
semihosting-Thumb_SVC Integer uint8_t 0xAB T32 SVC number for semihosting.
semihosting-cmd_linec String No limit except memory [Empty string] Command line available to semihosting SVC calls.
semihosting-enable Boolean true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-heap_base Integer 0x00000000-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit Integer 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base Integer 0x00000000-0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit Integer 0x00000000-0xFFFFFFFF 0x0F0000000 Virtual address of stack limit.
siliconID Integer uint32_t 0x41000000 Value as read by the system coprocessor siliconID register.
vfp-enable_at_resetd Boolean true, false false Enable coprocessor access and VFP at reset.
VINITHI Boolean true, false false Initialize with high vectors enabled.

ARMCortexA8CT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the coprocessor 14 registers, the integration and test registers, and the PLE model, which is register based and has no implemented behavior.

This PV model does not model Level 1 or Level 2 caches. The system coprocessor registers related to cache operations permit cache aware software to work, but in most cases they only check register access permissions:

  • Cache Dirty Status.
  • Data Memory Barrier.
  • Data Write Barrier.
  • ICache/DCache lockdown.
  • ICache/DCache master valid.
  • Invalidate and/or Clean Both Caches.
  • Invalidate and/or Clean Entire ICache/DCache.
  • Invalidate and/or Clean ICache/DCache by Index.
  • Invalidate and/or Clean ICache/DCache by MVA.
  • Level 1 System array debug registers.
  • Level 2 Cache Auxiliary control.
  • Level 2 Cache Lockdown.
  • Level 2 System array debug registers.
  • Prefetch ICache Line.
  • Preload Engine registers.


These TLB registers do not have working implementations:

  • D-TLB ATTR read/write.
  • D-TLB CAM read/write.
  • D-TLB PA read/write.
  • Normal memory remap register.
  • Primary memory remap register.

In addition, the simulation does not distinguish peripheral accesses from data accesses, so it ignores configuration of the peripheral port memory remap register.

ARMCortexA8CT - caches

This component implements a PV-accurate view of the L1 and L2 caches.

ARMCortexA8CT - debug features

This component exports a CADI debug interface.

ARMCortexA8CT - debug - registers

All core, VFP, and CP15 registers are visible in the debugger.

The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior.

ARMCortexA8CT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexA8CT - debug - memory

This component presents two 4GB views of virtual memory, one as seen from secure mode and one as seen from normal mode.

ARMCortexA8CT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of Linux on an example system.

ARMCortexA8CT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • There is a single memory port combining instruction, data, DMA and peripheral access.
  • The L2 cache write allocate policy is not configurable. It defaults to write-allocate. Writes to the configuration register succeed but are ignored, meaning that data can be unexpectedly stored in the L2 cache.
  • Unaligned accesses with the MMU disabled on the processor do not cause data aborts.
a If one cache is stateful, then the others must be too.
b Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.
c The value of argv[0] points to the first command line argument, not to the name of an image.
d This is a model specific behavior with no hardware equivalent.
Was this page helpful? Yes No