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ARMCortexA9UPCT component

This section describes the ARMCortexA9UPCT component.

ARMCortexA9UPCT - about

This C++ component is a model of r3p0 of a Cortex®-A9 processor.

ARMCortexA9UPCT - ports

This section describes the ports.

Table 3-42 ARMCortexA9UPCT ports

Name Protocol Type Description
cfgend[0] Signal Slave Initialize to BE8 endianness after a reset.
cfgnmfi[0] Signal Slave Enable nonmaskable FIQ interrupts after a reset.
clk_in ClockSignal Slave Main processor clock input.
clusterid Value Slave Value read in MPIDR register.
cp15sdisable[0] Signal Slave Disable write access to some cp15 registers.
event Signal Peer Event input and output for wakeup from WFE. This port amalgamates the EVENTI and EVENT0 signals that are present on hardware.
fiq[0] Signal Slave Processor FIQ signal input.
irq[0] Signal Slave Processor IRQ signal input.
pmuirq[0] Signal Master Performance Monitoring Unit (PMU) interrupt signal.
pvbus_m0 PVBus Master AXI master 0 bus master channel.
reset[0] Signal Slave Processor reset signal.
standbywfe[0] Signal Master Indicates if a processor is in WFE state.
standbywfi[0] Signal Master Indicates if a processor is in WFI state.
teinit[0] Signal Slave Initialize to take exceptions in T32 state after a reset.
ticks[0] InstructionCount Master Processor instruction count for visualization.
vinithi[0] Signal Slave Initialize with high vectors enabled after a reset.

ARMCortexA9UPCT - parameters

The parameters are set once.

The processor might have the instance name coretile.core.cpu0, for example.

Table 3-43 ARMCortexA9UPCT cluster parameters

Name Type Allowed values Default value Description
CLUSTER_ID int 0-15 0 Cluster ID value.
device-accurate-tlb bool true, false falsea Specify whether or not all TLBs are modeled.
dcache-state_modelled bool true, false false Set whether or not D-cache has stateful implementation.
icache-state_modelled bool true, false false Set whether or not I-cache has stateful implementation.

Table 3-44 ARMCortexA9UPCT core parameters

Name Type Allowed values Default value Description
ase-presentb bool true, false true Set whether or not model has NEON™ support.
CFGEND bool true, false false Initialize to BE8 endianness.
CFGNMFI bool true, false false Enable nonmaskable FIQ interrupts on startup.
CP15SDISABLE bool true, false false Initialize to disable access to some CP15 registers.
cpi_div int 1-0x7FFFFFFF 1 Divider for calculating Cycles Per Instruction (CPI).
cpi_mul int 1-0x7FFFFFFF 1 Multiplier for calculating CPI.
dcache-size int 16KB, 32KB, 64KB 0x8000 Set D-cache size in bytes.
icache-size int 16KB, 32KB, 64KB 0x8000 Set I-cache size in bytes.
min_sync_level int 0-3 0 Controls the minimum syncLevel.
POWERCTLI int 0-3 0 Default power control state for core.
semihosting-cmd_linec string No limit except memory [Empty string] Command line available to semihosting SVC calls.
semihosting-enable bool true, false true Enable semihosting SVC traps. Caution: applications that do not use semihosting must set this parameter to false.
semihosting-ARM_SVC int 0x000000-0xFFFFFF 0x123456 A32 SVC number for semihosting.
semihosting-Thumb_SVC int 0x00-0xFF 0xAB T32 SVC number for semihosting.
semihosting-heap_base int 0x00000000-0xFFFFFFFF 0x0 Virtual address of heap base.
semihosting-heap_limit int 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of top of heap.
semihosting-stack_base int 0x00000000-0xFFFFFFFF 0x10000000 Virtual address of base of descending stack.
semihosting-stack_limit int 0x00000000-0xFFFFFFFF 0x0F000000 Virtual address of stack limit.
TEINIT bool true, false false T32 exception enable. The default has exceptions including reset handled in A32 state.
vfp-enable_at_resetd bool true, false false Enable coprocessor access and VFP at reset.
vfp-presentb bool true, false true Set whether or not the model has VFP support.
VINITHI bool true, false false Initialize with high vectors enabled.

ARMCortexA9UPCT - registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the integration and test registers.

These TLB registers do not have working implementations:

  • Normal memory remap register.
  • Primary memory remap register.
  • Read Main TLB Entry.
  • Write Main TLB Entry.
  • Main TLB VA.
  • Main TLB PA.
  • Main TLB Attr.

In addition, the simulation does not distinguish peripheral accesses from data accesses, so it ignores configuration of the peripheral port memory remap register.

ARMCortexA9UPCT - caches

This component implements L1 cache as architecturally defined, but does not implement L2 cache. If you require L2 cache you can add a PL310 Level 2 Cache Controller component.

Cache and TLB component visibility

If a core model has a cache model available, to create it and make it visible, enable it. To enable the cache model and be ready to use cache CADI, set these model parameters:

  • l1_icache-state_modelled
  • l1_dcache-state_modelled

To use cache and TLB viewers, connect the cache and TLB CADI components.

ARMCortexA9UPCT - debug features

This component exports a CADI debug interface.

ARMCortexA9UPCT - debug - registers

All core, VFP, and CP15 registers are visible in the debugger.

ARMCortexA9UPCT - debug - breakpoints

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

ARMCortexA9UPCT - debug - memory

This component presents two 4GB views of virtual memory, one as seen from secure mode and one as seen from normal mode.

ARMCortexA9UPCT - verification and testing

This component passes tests by using the architecture validation suite tests and booting of Linux on an example system.

ARMCortexA9UPCT - differences between the CT model and RTL implementations

This component differs from the corresponding revision of the RTL implementation.

  • The RR bit in the SCTLR is ignored.
  • The Power Control Register in the system control coprocessor is implemented but writing to it does not change the behavior of the model.
  • The model cannot be configured with a 128-entry TLB.
a Specifying false models enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.
b  The ase-present and vfp-present parameters configure the synthesis options.
vfp present and ase present
NEON and VFPv3-D32 supported.
vfp present and ase not present
VFPv3-D16 supported.
vfp not present and ase present
Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support.
vfp not present and ase not present
Model has neither NEON nor VFPv3-D32 support.
c The value of argv[0] points to the first command line argument, not to the name of an image.
d This is a model specific behavior with no hardware equivalent.
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