You copied the Doc URL to your clipboard.

ARMCortexM23CT component

This section describes the ARMCortexM23CT component.

ARMCortexM23CT - about

ARMCortexM23CT processor component. This model is written in C++.

ARMCortexM23CT contains the following CADI targets:

  • ARM_CortexM23

ARMCortexM23CT - ports

This section describes the ports.

Table 3-87 Ports

Name Protocol Type Description
ahbd PVBus Slave Debug AHB. Core bus slave that is driven by the DAP.
auxfault Value Slave This port is wired to the Auxiliary Fault Status Register.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal that is connected to the clk_in port is used to determine the rate at which the processor executes instructions.
cpuwait Signal Slave Checked at time of reset. If true, it keeps the processor in wait state. This port has no effect when the processor starts execution. (In signal.)
currpri Value Master Current execution priority.
dap_s PVBus Slave Debug Access Port (DAP).
dbgen Signal Slave Invasive debug control signals.
dbgrestart Signal Slave Request from external debugger for processor to exit halt mode. (In signal.)
dbgrestarted Signal Master Inform external debugger that the processor completed the dbgrestart request. (Out signal.)
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
halted Signal Master Indicates whether the processor is in halt mode. An external debugger can read this port. (In signal.)
hreset Signal Slave Raising this signal puts the processor into reset mode, but does not reset the debug logic.
initvtor Value Slave Reset configuration port - Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset. This port remains functional whether ARMv8-M Security Extensions are included or not. When ARMv8-M Security Extensions are not included, all exceptions use the Non-secure vector base address that is given by this port.
initvtorns Value Slave Reset configuration port - Non-secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset. This port becomes functional when ARMv8-M Security Extensions are included. When ARMv8-M Security Extensions are not included, this port is ignored.
io_port_in PVBus Slave I/O port pair. Used if IOP is true. To emulate an I/O Port peripheral which handles a range of addresses, implement a component which accepts all transactions from io_port_out and forwards transactions with addresses outside the range of interest to io_port_in (for example a component derived from pv::RemapTransactionIntermediary). If io_port_out is connected to io_port_in, the I/O Port is circumvented.
io_port_out PVBus Master I/O port pair. Used if IOP is true. To emulate an I/O Port peripheral which handles a range of addresses, implement a component which accepts all transactions from io_port_out and forwards transactions with addresses outside the range of interest to io_port_in (for example a component derived from pv::RemapTransactionIntermediary). If io_port_out is connected to io_port_in, the I/O Port is circumvented.
irq Signal Slave This signal array delivers signals to the NVIC.
lockup Signal Master Asserted when the processor is in lockup state.
niden Signal Slave Non-invasive debug enable.
nmi Signal Slave Configure nonmaskable interrupt.
poreset Signal Slave Raising this signal does a power-on reset of the processor.
pv_ppbus_m PVBus Master The processor generates External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The processor generates bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
spiden Signal Slave Secure privileged invasive debug enable.
spniden Signal Slave Secure privileged non-invasive debug enable.
stcalib Value Slave This port is the calibration value for the Secure SysTick timer. When ARMv8-M Security Extensions are not included, this port is the only calibration value for the SysTick timer.
stcalibns Value Slave This port is the calibration value for the Non-secure SysTick timer. When ARMv8-M Security Extensions are not included, this port is ignored.
stclk ClockSignal Slave This port is the reference clock for the SysTick timer.
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the processor.

ARMCortexM23CT - parameters

This section describes the parameters.

Table 3-88 Parameters

Name Type Default value Description
BE bool 0x0 Initialize processor to big endian mode.
BKPT int 0x4 Number of breakpoint unit comparators implemented.
DBG bool 0x1 Set whether debug extensions are implemented.
IDAU_REGIONn.BADDR int 0x0 Base address of IDAU regionn, where 0 ≤ n ≤ 31.
IDAU_REGIONn.ENABLE bool 0x0 0 ≤ n ≤ 31.
0
IDAU regionn is Secure, or absent if LADDR=0.
1
IDAU regionn is Non-secure, Non-secure callable (NSC), or exempt from attribution check.
IDAU_REGIONn.EXEMPT bool 0x0 Mark IDAU regionn as exempt, where 0 ≤ n ≤ 31.
IDAU_REGIONn.LADDR int 0x0 Limit address of IDAU regionn, where 0 ≤ n ≤ 31.
IDAU_REGIONn.NSC bool 0x0 Set NSC for IDAU regionn, where 0 ≤ n ≤ 31.
INITVTOR int 0x0 Secure vector-table offset at reset.
INITVTORNS int 0x0 Non-secure vector-table offset at reset.
IOP bool 0x0 Send all d-side transactions to the port io_port_out. Transactions which do not match are returned to the port io_port_in.
IRQDISn int 0x0 IRQ line disable mask. Bit N of this 32-bit parameter disables IRQ[N+(32xn)], where 0 ≤ n ≤ 7.
MPU_NS int 0x8 Number of regions in the Non-secure MPU. If Security Extensions are absent, this parameter is the total number of MPU regions.
MPU_S int 0x8 Number of regions in the Secure MPU. If Security Extensions are absent, this parameter is ignored.
NUMIRQ int 0x16 Number of user interrupts.
NUM_IDAU_REGION int 0x0 Number of IDAU regions (0 if no IDAU). The IDAU is equivalent to an architectural SAU with ALLNS set to 0 and no register access.
SAU int 0x4 Number of SAU regions (0 if no SAU).
SAU_CTRL.ALLNS bool 0x0 At reset, the SAU treats the entire memory space as Non-secure when the SAU is disabled if this parameter is set.
SAU_CTRL.ENABLE bool 0x0 Enable SAU at reset.
SAU_REGIONn.BADDR int 0x0 Base address of SAU regionn at reset, where 0 ≤ n ≤ 7.
SAU_REGIONn.ENABLE bool 0x0 Enable SAU regionn at reset, where 0 ≤ n ≤ 7.
SAU_REGIONn.LADDR int 0x0 Limit address of SAU regionn at reset, where 0 ≤ n ≤ 7.
SAU_REGIONn.NSC bool 0x0 Set NSC for SAU regionn at reset, where 0 ≤ n ≤ 7.
SECEXT bool 0x1 Whether the ARMv8-M Security Extensions are included.
SYST int 0x2 Include SysTick timer functionality:
0
Absent
1
Secure only
2
Secure and Non-secure
VTOR bool 0x1 Include Vector Table Offset Register.
WIC bool 0x1 Include support for WIC-mode deep sleep.
WPT int 0x4 Number of watchpoint unit comparators implemented.
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction).
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction).
ignore-SCR.SLEEPONEXIT bool 0x0 Never sleep on exit from handler to thread mode.
master_id int 0x0 Master ID presented in bus transactions.
min_sync_level int 0x0 Force minimum syncLevel:
0
off (default)
1
syncState
2
postInsnIO
3
postInsnAll
scheduler_mode int 0x0 Control the interleaving of instructions in this processor:
0
Default long quantum.
1
Low latency mode, short quantum, and signal checking.
2
Lock-breaking mode, long quantum with additional context switches near load-exclusive instructions.
3
ISSCompare
semihosting-Thumb_SVC int 0x171 T32 SVC number for semihosting.
semihosting-cmd_line string "" Command line available to semihosting SVC calls.
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base.
semihosting-heap_limit int 0x275775488 Virtual address of top of heap.
semihosting-stack_base int 0x275775488 Virtual address of base of descending stack.
semihosting-stack_limit int 0x276824064 Virtual address of stack limit.

ARMCortexM23CT - registers

This section describes the registers.

Table 3-89 Registers in Core group

Name Width Reset value Description
BASEPRI_NS 32 0x0 BASEPRI_NS
BASEPRI_S 32 0x0 BASEPRI_S
CONTROL_NS 32 0x0 CONTROL_NS
CONTROL_S 32 0x0 CONTROL_S
FAULTMASK_NS 32 0x0 FAULTMASK_NS
FAULTMASK_S 32 0x0 FAULTMASK_S
PRIMASK_NS 32 0x0 PRIMASK_NS
PRIMASK_S 32 0x0 PRIMASK_S
Rn 32 0x0 Rn, where 0 ≤ n ≤ 15.
R13_MAIN_NS 32 0x0 MSP_NS
R13_MAIN_S 32 0x0 MSP_S
R13_PROCESS_NS 32 0x0 PSP_NS
R13_PROCESS_S 32 0x0 PSP_S
XPSR 32 0xf1000000 XPSR

Table 3-90 Registers in DWT group

Name Width Reset value Description
DWT_COMPn 32 0x0 DWT Comparator Register n, where 0 ≤ n ≤ 3.
DWT_CPICNT 32 0x0 DWT CPI Counter (values are indicative and will not be the same as hardware)
DWT_CTRL 32 0x4b000000 DWT Control Register
DWT_CYCCNT 32 0x0 DWT Cycle Counter (values are indicative and will not be the same as hardware)
DWT_EXCCNT 32 0x0 DWT Exception Overhead Counter (values are indicative and will not be the same as hardware)
DWT_FOLDCNT 32 0x0 DWT Instruction-Fold Counter (values are indicative and will not be the same as hardware)
DWT_FUNCTION0 32 0x50000000 DWT Function Register 0
DWT_FUNCTION1 32 0xd0000000 DWT Function Register 1
DWT_FUNCTION2 32 0x50000000 DWT Function Register 2
DWT_FUNCTION3 32 0xd0000000 DWT Function Register 3
DWT_LAR 32 0x0 DWT Lock Access Register
DWT_LSR 32 0x3 DWT Lock Status Register
DWT_LSUCNT 32 0x0 DWT LSU-overhead Counter (values are indicative and will not be the same as hardware)
DWT_PCSR 32 0x0 DWT PC-Sample Register
DWT_SLEEPCNT 32 0x0 DWT Sleep/WFE/WFI Counter
ETMDEVAFF0 32 0x0 Device Affinity 0
ETMDEVAFF1 32 0x0 Device Affinity 1
ETMDEVARCH 32 0x0 Device Architecture
ETMTRCACATRnH 32 0x0 Address Comparator Access Type nH, where 0 ≤ n ≤ 15.
ETMTRCACATRnL 32 0x0 Address Comparator Access Type nL, where 0 ≤ n ≤ 15.
ETMTRCACVRnH 32 0x0 Address Comparator Value nH, where 0 ≤ n ≤ 15.
ETMTRCACVRnL 32 0x0 Address Comparator Value nL, where 0 ≤ n ≤ 15.
ETMTRCAUTHSTATUS 32 0x0 Authentication Status
ETMTRCAUXCTLR 32 0x0 Auxiliary Control
ETMTRCBBCTLR 32 0x0 Branch Broadcast Control
ETMTRCCCCTLR 32 0x0 Cycle Count Control
ETMTRCCIDCCTLR0 32 0x0 Context ID Comparator Control 0
ETMTRCCIDCCTLR1 32 0x0 Context ID Comparator Control 1
ETMTRCCIDCVRnH 32 0x0 ETMTRCCIDCVRnH, where 0 ≤ n ≤ 7.
ETMTRCCIDCVRnL 32 0x0 ETMTRCCIDCVRnL, where 0 ≤ n ≤ 7.
ETMTRCCIDRn 32 0x0 Component IDn, where 0 ≤ n ≤ 3.
ETMTRCCLAIMCLR 32 0x0 Claim Tag Clear
ETMTRCCLAIMSET 32 0x0 Claim Tag Set
ETMTRCCNTCTLRn 32 0x0 Counter Control n, where 0 ≤ n ≤ 2.
ETMTRCCNTRLDVRn 32 0x0 Counter Reload Value n, where 0 ≤ n ≤ 2.
ETMTRCCNTVRn 32 0x0 Counter Value Register n, where 0 ≤ n ≤ 2.
ETMTRCCONFIGR 32 0x0 Trace Configuration
ETMTRCDEVID 32 0x0 Device ID
ETMTRCDEVTYPE 32 0x0 Device Type
ETMTRCDVCMRnH 32 0x0 Data Value Comparator Mask nH, where 0 ≤ n ≤ 7.
ETMTRCDVCMRnL 32 0x0 Data Value Comparator Mask nL, where 0 ≤ n ≤ 7.
ETMTRCDVCVRnH 32 0x0 Data Value Comparator Value nH, where 0 ≤ n ≤ 7.
ETMTRCDVCVRnL 32 0x0 Data Value Comparator Value nL, where 0 ≤ n ≤ 7.
ETMTRCEVENTCTL0R 32 0x0 Event Control 0
ETMTRCEVENTCTL1R 32 0x0 Event Control 1
ETMTRCEXTINSELR 32 0x0 External Input Select
ETMTRCIDRn 32 0x0 ID n, where 0 ≤ n ≤ 13.
ETMTRCIMSPECn 32 0x0 Implementation Specific n, where 0 ≤ n ≤ 7.
ETMTRCITCTRL 32 0x0 Integration Mode Control
ETMTRCLAR 32 0x0 Software Lock Access
ETMTRCLSR 32 0x0 Software Lock Status
ETMTRCOSLAR 32 0x0 OS Lock Access
ETMTRCOSLSR 32 0x0 OS Lock Status
ETMTRCPDCR 32 0x0 Powerdown Control
ETMTRCPDSR 32 0x0 Powerdown Status
ETMTRCPIDRn 32 0x0 Peripheral IDn, where 0 ≤ n ≤ 7.
ETMTRCPRGCTLR 32 0x0 Programming Control
ETMTRCPROCSELR 32 0x0 Processor Select Control
ETMTRCSEQEVRn 32 0x0 Sequencer State Transition Control n, where 0 ≤ n ≤ 2.
ETMTRCSEQRSTEVR 32 0x0 Sequencer Reset Control
ETMTRCSEQSTR 32 0x0 Sequencer State Register
ETMTRCSTALLCTLR 32 0x0 Stall Control
ETMTRCSTATR 32 0x0 Status
ETMTRCSYNCPR 32 0x0 Synchronization Period
ETMTRCTRACEIDR 32 0x0 Trace ID
ETMTRCTSCTLR 32 0x0 Global Timestamp Control
ETMTRCVDARCCTLR 32 0x0 ViewData Include/Exclude Address Range Comparator Control
ETMTRCVDCTLR 32 0x0 ViewData Main Control
ETMTRCVDSACCTLR 32 0x0 ViewData Include/Exclude Single Address Comparator Control
ETMTRCVICTLR 32 0x0 ViewInst Main Control
ETMTRCVIIECTLR 32 0x0 ViewInst Include/Exclude Control
ETMTRCVIPCSSCTLR 32 0x0 ViewInst Start/Stop Processor Comparator Control
ETMTRCVISSCTLR 32 0x0 ViewInst Start/Stop Control
ETMTRCVMIDCCTLR0 32 0x0 Virtual Machine ID Comparator Control 0
ETMTRCVMIDCCTLR1 32 0x0 Virtual Machine ID Comparator Control 1
ETMTRCVMIDCVRnH 32 0x0 ETMTRCVMIDCVRnH, where 0 ≤ n ≤ 7.
ETMTRCVMIDCVRnL 32 0x0 ETMTRCVMIDCVRnL, where 0 ≤ n ≤ 7.

Table 3-91 Registers in Debug group

Name Width Reset value Description
DAUTHCTRL 32 0x0 Debug Authentication Control
DCRDR 32 0x0 Debug Core Register Data Register
DCRSR 32 0x0 Debug Core Register Select Register
DEMCR 32 0x0 Debug Exception and Monitor Control Register
DFSR 32 0x0 Debug Fault Status Register
DHCSR 32 0x3010000 Debug Halting Control and Status Register
DSCSR 32 0x10001 Debug Security Control and Status Register

Table 3-92 Registers in FPB group

Name Width Reset value Description
FP_COMPn 32 0x0 Flash Patch Comparator Register n, where 0 ≤ n ≤ 3.
FP_CTRL 32 0x10000040 Flash Patch Control Register
FP_LAR 32 0x0 Flash Patch Lock Access Register
FP_LSR 32 0x3 Flash Patch Lock Status Register
FP_REMAP 32 0x0 Flash Patch Remap Register

Table 3-93 Registers in ID group

Name Width Reset value Description
CID0 32 0xd Component ID Register 0
CID1 32 0x90 Component ID Register 1
CID2 32 0x5 Component ID Register 2
CID3 32 0xb1 Component ID Register 3
CPUID 32 0x411cd200 CPUID base register
DWT_DEVARCH 32 0x47701a02 DWT DEVARCH Register
FP_DEVARCH 32 0x47701a03 FP DEVARCH Register
MCD_DEVARCH 32 0x47702a04 MicroController Debug DEVARCH Register
PID0 32 0x1 Peripheral ID Register 0
PID1 32 0xb0 Peripheral ID Register 1
PID2 32 0xb Peripheral ID Register 2
PID3 32 0x0 Peripheral ID Register 3
PID4 32 0x4 Peripheral ID Register 4
PID5 32 0x0 Peripheral ID Register 5
PID6 32 0x0 Peripheral ID Register 6
PID7 32 0x0 Peripheral ID Register 7

Table 3-94 Registers in Internal State group

Name Width Reset value Description
SECURITY_STATE 1 0x0 Security state
SEV_STATE 1 0x0 SEV/WFE event state
WAKE_WFI_NOW 1 0x0 Command to wake the processor from WFI state.
WFI_WAKEUP 1 0x0 WFI state
WFX_OVERRIDE 2 0x0 Override WFx behavior in ISSCompare environment.

Table 3-95 Registers in MPU group

Name Width Reset value Description
MPU_CTRL_NS 32 0x0 Non-secure MPU Control Register
MPU_CTRL_S 32 0x0 Secure MPU Control Register
MPU_MAIR0_NS 32 0x0 Non-secure MPU Memory Attribute Indirection Register 0
MPU_MAIR0_S 32 0x0 Secure MPU Memory Attribute Indirection Register 0
MPU_MAIR1_NS 32 0x0 Non-secure MPU Memory Attribute Indirection Register 1
MPU_MAIR1_S 32 0x0 Secure MPU Memory Attribute Indirection Register 1
MPU_RBARn_NS 32 0x0 Non-secure MPU Region Base Address Register n, where 0 ≤ n ≤ 7.
MPU_RBARn_S 32 0x0 Secure MPU Region Base Address Register n, where 0 ≤ n ≤ 7.
MPU_RBAR_NS 32 0x0 Non-secure MPU Region Base Address Register
MPU_RBAR_S 32 0x0 Secure MPU Region Base Address Register
MPU_RLARn_NS 32 0x0 Non-secure MPU Region Limit Address Register n, where 0 ≤ n ≤ 7.
MPU_RLARn_S 32 0x0 Secure MPU Region Limit Address Register n, where 0 ≤ n ≤ 7.
MPU_RLAR_NS 32 0x0 Non-secure MPU Region Limit Address Register
MPU_RLAR_S 32 0x0 Secure MPU Region Limit Address Register
MPU_RNR_NS 32 0x0 Non-secure MPU Region Number Register
MPU_RNR_S 32 0x0 Secure MPU Region Number Register
MPU_TYPE_NS 32 0x800 Non-secure MPU Type Register
MPU_TYPE_S 32 0x800 Secure MPU Type Register

Table 3-96 Registers in NVIC group

Name Width Reset value Description
NVIC_IABR0 32 0x0 NVIC IRQ Active Bit Register 0
NVIC_ICER0 32 0x0 NVIC IRQ Clear Enable Register 0
NVIC_ICPR0 32 0x0 NVIC IRQ Clear Pending Register 0
NVIC_IPRn 32 0x0 NVIC IRQ Priority Register n, where 0 ≤ n ≤ 7.
NVIC_ISER0 32 0x0 NVIC IRQ Set Enable Register 0
NVIC_ISPR0 32 0x0 NVIC IRQ Set Pending Register 0
NVIC_ITNS0 32 0x0 NVIC IRQ Targets Non-secure State Register 0

Table 3-97 Registers in SAU group

Name Width Reset value Description
SAU_CTRL 32 0x0 SAU Control Register
SAU_RBAR 32 0x0 SAU Region Base Address Register
SAU_RBARn 32 0x0 SAU Region Base Address Register n, where 0 ≤ n ≤ 3.
SAU_RLAR 32 0x0 SAU Region Limit Address Register
SAU_RLARn 32 0x0 SAU Region Limit Address Register n, where 0 ≤ n ≤ 3.
SAU_RNR 32 0x0 SAU Region Number Register
SAU_TYPE 32 0x4 SAU Type Register

Table 3-98 Registers in Simulation group

Name Width Reset value Description
coreRunState 32 0x0 Core run state:
0
Unknown
1
Running
2
Halted
3
Standby WFE
4
Standby WFI
5
In Reset
6
Dormant
7
Shutdown
memoryBptAccessRW 32 0x0 Last memory breakpoint hit access type:
0
none
1
read
2
write
3
rw
memoryBptAccessSize 32 0x0 Last memory breakpoint hit access size in bytes.
memoryBptAccessVA 32 0x0 Last memory breakpoint hit access virtual address.
memoryBptPC 32 0x0 Last memory breakpoint hit PC.
minSyncLevel 32 0x0 Minimum syncLevel.
semihostAction 32 0x0 Semihost action:
0
unknown
1
fall through
2
intercepted
3
intercepted and stepback
syncLevel 32 0x0 Read-only: current syncLevel (0-3)
syncLevelPostInsnAllCount 32 0x0 Current number of users for SL_POST_INSN_ALL (treat as read-only).
syncLevelPostInsnAllRegister 32 0x0 Write-only: register a new user for syncLevel SL_POST_INSN_ALL
syncLevelPostInsnAllUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_POST_INSN_ALL
syncLevelPostInsnIOCount 32 0x0 Current number of users for SL_POST_INSN_IO (treat as read-only).
syncLevelPostInsnIORegister 32 0x0 Write-only: register a new user for syncLevel SL_POST_INSN_IO
syncLevelPostInsnIOUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_POST_INSN_IO
syncLevelSyncStateCount 32 0x0 Current number of users for SL_SYNC_STATE (treat as read-only).
syncLevelSyncStateRegister 32 0x0 Write-only: register a new user for syncLevel SL_SYNC_STATE
syncLevelSyncStateUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_SYNC_STATE

Table 3-99 Registers in Stack Limits group

Name Width Reset value Description
MSPLIM_NS 32 0x0 MSPLIM (Non-secure state)
MSPLIM_S 32 0x0 MSPLIM (Secure state)
MSP_NS 32 0x0 MSP (Non-secure state)
MSP_S 32 0x0 MSP (Secure state)
PSPLIM_NS 32 0x0 PSPLIM (Non-secure state)
PSPLIM_S 32 0x0 PSPLIM (Secure state)
PSP_NS 32 0x0 PSP (Non-secure state)
PSP_S 32 0x0 PSP (Secure state)

Table 3-100 Registers in SysTick group

Name Width Reset value Description
SYST_CALIB_NS 32 0x0 SysTick Calibration Value Register (Non-secure state)
SYST_CALIB_S 32 0x0 SysTick Calibration Value Register (Secure state)
SYST_CSR_NS 32 0x0 SysTick Control and Status Register (Non-secure state)
SYST_CSR_S 32 0x0 SysTick Control and Status Register (Secure state)
SYST_CVR_NS 32 0x0 SysTick Current Value Register (Non-secure state)
SYST_CVR_S 32 0x0 SysTick Current Value Register (Secure state)
SYST_RVR_NS 32 0x0 SysTick Reload Value Register (Non-secure state)
SYST_RVR_S 32 0x0 SysTick Reload Value Register (Secure state)

Table 3-101 Registers in System Control group

Name Width Reset value Description
ACTLR_NS 32 0x0 Auxiliary Control Register (Non-secure state)
ACTLR_S 32 0x0 Auxiliary Control Register (Secure state)
AIRCR 32 0xfa050000 Application Interrupt and Reset Control Register
CCR_NS 32 0x209 Configuration and Control Register (Non-secure state)
CCR_S 32 0x209 Configuration and Control Register (Secure state)
ICSR_NS 32 0x0 Interrupt Control and State Register (Non-secure state)
ICSR_S 32 0x0 Interrupt Control and State Register (Secure state)
ICTR 32 0x0 Interrupt Controller Type Register
SCR_NS 32 0x0 System Control Register (Non-secure state)
SCR_S 32 0x0 System Control Register (Secure state)
SHCSR_NS 32 0x0 System Handler Control and State Register (Non-secure state)
SHCSR_S 32 0x0 System Handler Control and State Register (Secure state)
SHPR1_NS 32 0x0 System Handler Priority Register 1 (Non-secure state)
SHPR1_S 32 0x0 System Handler Priority Register 1 (Secure state)
SHPR2_NS 32 0x0 System Handler Priority Register 2 (Non-secure state)
SHPR2_S 32 0x0 System Handler Priority Register 2 (Secure state)
SHPR3_NS 32 0x0 System Handler Priority Register 3 (Non-secure state)
SHPR3_S 32 0x0 System Handler Priority Register 3 (Secure state)
VTOR_NS 32 0x0 Vector Table Offset Register (Non-secure state)
VTOR_S 32 0x0 Vector Table Offset Register (Secure state)
Was this page helpful? Yes No