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ARMSC000CT component

This section describes the ARMSC000CT component.

ARMSC000CT - about

ARM® SecurCore® SC000 processor component. This model is written in C++ and models version r0p1 of the RTL.

ARMSC000CT contains the following CADI targets:

  • ARM_SC000

The model has the following limitations:

  • It does not implement any security features.
  • Only bit[0] of the Auxiliary Control Register is supported for read/write. No functionality is implemented.
  • The Security Features Control Register read/write access is supported using SECKEY. No functionality is implemented.

ARMSC000CT - ports

This section describes the ports.

Table 3-116 Ports

Name Protocol Type Description
auxfault Value Slave This port is wired to the Auxiliary Fault Status Register.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal that is connected to the clk_in port is used to determine the rate at which the processor executes instructions.
currpri Value Master Current execution priority.
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
intisr Signal Slave This signal array delivers signals to the NVIC.
intnmi Signal Slave Configure nonmaskable interrupt.
io_port_in PVBus Slave I/O port pair. Used if IOP is true. To emulate an I/O Port peripheral which handles a range of addresses, implement a component which accepts all transactions from io_port_out and forwards transactions with addresses outside the range of interest to io_port_in (for example a component derived from pv::RemapTransactionIntermediary). If io_port_out is connected to io_port_in, the I/O Port is circumvented.
io_port_out PVBus Master I/O port pair. Used if IOP is true. To emulate an I/O Port peripheral which handles a range of addresses, implement a component which accepts all transactions from io_port_out and forwards transactions with addresses outside the range of interest to io_port_in (for example a component derived from pv::RemapTransactionIntermediary). If io_port_out is connected to io_port_in, the I/O Port is circumvented.
lockup Signal Master Asserted when the processor is in lockup state.
poreset Signal Slave Raising this signal does a powerup reset of the core.
pv_ppbus_m PVBus Master The processor generates External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The processor generates bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
stcalib Value Slave This port is the calibration value for the SysTick timer.
stclk ClockSignal Slave This port is the reference clock for the SysTick timer.
sysreset Signal Slave Raising this signal puts the processor into reset mode, but does not reset the debug logic.
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the processor.

ARM_SC000 - registers

This section describes the registers.

Table 3-117 Registers in Core group

Name Width Reset value Description
BASEPRI 32 0x0 BASEPRI
CONTROL 32 0x0 CONTROL
FAULTMASK 32 0x0 FAULTMASK
PRIMASK 32 0x0 PRIMASK
Rn 32 0x0 Rn, where 0 ≤ n ≤ 15.
R13_MAIN 32 0x0 MSP
R13_PROCESS 32 0x0 PSP
XPSR 32 0x1000000 XPSR

Table 3-118 Registers in DWT group

Name Width Reset value Description
DWT_COMP0 32 0x0 DWT Comparator Register 0
DWT_COMP1 32 0x0 DWT Comparator Register 1
DWT_CPICNT 32 0x0 DWT CPI Counter (values are indicative and will not be the same as hardware)
DWT_CTRL 32 0x20000000 DWT Control Register
DWT_CYCCNT 32 0x0 DWT Cycle Counter (values are indicative and will not be the same as hardware)
DWT_EXCCNT 32 0x0 DWT Exception Overhead Counter (values are indicative and will not be the same as hardware)
DWT_FOLDCNT 32 0x0 DWT Instruction-Fold Counter (values are indicative and will not be the same as hardware)
DWT_FUNCTION0 32 0x200 DWT Function Register 0
DWT_FUNCTION1 32 0x200 DWT Function Register 1
DWT_LAR 32 0x0 DWT Lock Access Register
DWT_LSR 32 0x3 DWT Lock Status Register
DWT_LSUCNT 32 0x0 DWT LSU-overhead Counter (values are indicative and will not be the same as hardware)
DWT_MASK0 32 0x0 DWT Mask Register 0
DWT_MASK1 32 0x0 DWT Mask Register 1
DWT_PCSR 32 0x0 DWT PC-Sample Register
DWT_SLEEPCNT 32 0x0 DWT Sleep/WFE/WFI Counter

Table 3-119 Registers in Debug group

Name Width Reset value Description
DCRDR 32 0x0 Debug Core Register Data Register
DCRSR 32 0x0 Debug Core Register Select Register
DEMCR 32 0x0 Debug Exception and Monitor Control Register
DFSR 32 0x0 Debug Fault Status Register
DHCSR 32 0x3010000 Debug Halting Control and Status Register

Table 3-120 Registers in FPB group

Name Width Reset value Description
FP_COMPn 32 0x0 Flash Patch Comparator Register n, where 0 ≤ n ≤ 3.
FP_CTRL 32 0x40 Flash Patch Control Register
FP_LAR 32 0x0 Flash Patch Lock Access Register
FP_LSR 32 0x3 Flash Patch Lock Status Register
FP_REMAP 32 0x0 Flash Patch Remap Register

Table 3-121 Registers in ID group

Name Width Reset value Description
CID0 32 0xd Component ID Register 0
CID1 32 0xe0 Component ID Register 1
CID2 32 0x5 Component ID Register 2
CID3 32 0xb1 Component ID Register 3
CPUID 32 0x410cc300 CPUID base register
PID0 32 0x0 Peripheral ID Register 0
PID1 32 0xb0 Peripheral ID Register 1
PID2 32 0xb Peripheral ID Register 2
PID3 32 0x0 Peripheral ID Register 3
PID4 32 0x4 Peripheral ID Register 4
PID5 32 0x0 Peripheral ID Register 5
PID6 32 0x0 Peripheral ID Register 6
PID7 32 0x0 Peripheral ID Register 7

Table 3-122 Registers in Internal State group

Name Width Reset value Description
SEV_STATE 1 0x0 SEV/WFE event state
WAKE_WFI_NOW 1 0x0 Command to wake the processor from WFI state.
WFI_WAKEUP 1 0x0 WFI state
WFX_OVERRIDE 2 0x0 Override WFx behavior in ISSCompare environment.

Table 3-123 Registers in MPU group

Name Width Reset value Description
MPU_CTRL 32 0x0 MPU Control Register
MPU_RASR 32 0x0 MPU Region Attribute and Size Register
MPU_RBAR 32 0x0 MPU Region Base Address Register
MPU_RNR 32 0x0 MPU Region Number Register
MPU_TYPE 32 0x0 MPU Type Register

Table 3-124 Registers in NVIC group

Name Width Reset value Description
NVIC_ICER 32 0x0 NVIC IRQ Clear Enable Register
NVIC_ICPR 32 0x0 NVIC IRQ Clear Pending Register
NVIC_IPRn 32 0x0 NVIC IRQ Priority Register n, where 0 ≤ n ≤ 7.
NVIC_ISER 32 0x0 NVIC IRQ Set Enable Register
NVIC_ISPR 32 0x0 NVIC IRQ Set Pending Register

Table 3-125 Registers in Simulation group

Name Width Reset value Description
coreRunState 32 0x0 Core run state:
0
Unknown
1
Running
2
Halted
3
Standby WFE
4
Standby WFI
5
In Reset
6
Dormant
7
Shutdown
memoryBptAccessRW 32 0x0 Last memory breakpoint hit access type:
0
none
1
read
2
write
3
rw
memoryBptAccessSize 32 0x0 Last memory breakpoint hit access size in bytes.
memoryBptAccessVA 32 0x0 Last memory breakpoint hit access virtual address.
memoryBptPC 32 0x0 Last memory breakpoint hit PC.
minSyncLevel 32 0x0 Minimum syncLevel
semihostAction 32 0x0 Semihost action:
0
unknown
1
fall through
2
intercepted
3
intercepted and stepback
syncLevel 32 0x0 Read-only: current syncLevel (0-3)
syncLevelPostInsnAllCount 32 0x0 Current number of users for SL_POST_INSN_ALL (treat as read-only).
syncLevelPostInsnAllRegister 32 0x0 Write-only: register a new user for syncLevel SL_POST_INSN_ALL.
syncLevelPostInsnAllUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_POST_INSN_ALL.
syncLevelPostInsnIOCount 32 0x0 Current number of users for SL_POST_INSN_IO (treat as read-only).
syncLevelPostInsnIORegister 32 0x0 Write-only: register a new user for syncLevel SL_POST_INSN_IO.
syncLevelPostInsnIOUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_POST_INSN_IO.
syncLevelSyncStateCount 32 0x0 Current number of users for SL_SYNC_STATE (treat as read-only).
syncLevelSyncStateRegister 32 0x0 Write-only: register a new user for syncLevel SL_SYNC_STATE
syncLevelSyncStateUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_SYNC_STATE

Table 3-126 Registers in Stack Limits group

Name Width Reset value Description
MSP 32 0x0 MSP
PSP 32 0x0 PSP

Table 3-127 Registers in SysTick group

Name Width Reset value Description
SYST_CALIB 32 0x0 SysTick Calibration Value Register
SYST_CSR 32 0x0 SysTick Control and Status Register
SYST_CVR 32 0x0 SysTick Current Value Register
SYST_RVR 32 0x0 SysTick Reload Value Register

Table 3-128 Registers in System Control group

Name Width Reset value Description
ACTLR 32 0x0 Auxiliary Control Register
AIRCR 32 0x0 Application Interrupt and Reset Control Register
CCR 32 0x208 Configuration and Control Register
ICSR 32 0x0 Interrupt Control and State Register
ICTR 32 0x0 Interrupt Controller Type Register
SCR 32 0x0 System Control Register
SFCR 32 0x0 Security Features Control Register. Read/write access is supported using SECKEY. No functionality is implemented.
SHCSR 32 0x0 System Handler Control and State Register
SHPR1 32 0x0 System Handler Priority Register 1
SHPR2 32 0x0 System Handler Priority Register 2
SHPR3 32 0x0 System Handler Priority Register 3
VTOR 32 0x0 Vector Table Offset Register

ARM_SC000 - parameters

This section describes the parameters.

Table 3-129 Parameters

Name Type Default value Description
BIGENDINIT bool 0x0 Initialize processor to big endian mode.
BKPT int 0x4 Number of breakpoint unit comparators implemented.
DBG bool 0x1 Set whether debug extensions are implemented.
IOP bool 0x0 Send all d-side transactions to the port io_port_out. Transactions which do not match are returned to the port io_port_in.
IRQDIS int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n].
NUM_IRQ int 0x20 Number of user interrupts.
NUM_MPU_REGION int 0x0 Number of MPU regions.
SYST bool 0x1 Enable support for SysTick timer functionality.
USER bool 0x1 Enable support for Unprivileged/Privileged Extension.
VTOR bool 0x1 Include Vector Table Offset Register.
WIC bool 0x1 Include support for WIC-mode deep sleep.
WPT int 0x2 Number of watchpoint unit comparators implemented.
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction).
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction).
master_id int 0x0 Master ID presented in bus transactions.
min_sync_level int 0x0 Force minimum syncLevel:
0
off (default)
1
syncState
2
postInsnIO
3
postInsnAll
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting.
semihosting-cmd_line string "" Command line available to semihosting SVC calls.
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base.
semihosting-heap_limit int 0x10700000 Virtual address of top of heap.
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack.
semihosting-stack_limit int 0x10800000 Virtual address of stack limit.
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