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ARMSC300CT component

This section describes the ARMSC300CT component.

ARMSC300CT - about

ARM® SecurCore® SC300 processor component. This model is written in C++ and models version r0p1 of the RTL.

ARMSC300CT contains the following CADI targets:

  • ARM_SC300

The model has the following limitations:

  • It does not implement any security features.
  • The Trash Register is implemented as RAZ/WI.
  • Only bit[0] of the Auxiliary Control Register is supported for read/write. No functionality is implemented.
  • The Security Features Control Register read/write access is supported using SECKEY. No functionality is implemented.

ARMSC300CT - ports

This section describes the ports.

Table 3-130 Ports

Name Protocol Type Description
auxfault Value Slave This port is wired to the Auxiliary Fault Status Register.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal that is connected to the clk_in port is used to determine the rate at which the processor executes instructions.
currpri Value Master Current execution priority.
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
intisr Signal Slave This signal array delivers signals to the NVIC.
intnmi Signal Slave Configure non maskable interrupt.
lockup Signal Master Asserted when the processor is in lockup state.
poreset Signal Slave Raising this signal does a powerup reset of the core.
pv_ppbus_m PVBus Master The processor generates External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The processor generates bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
stcalib Value Slave This port is the calibration value for the SysTick timer.
stclk ClockSignal Slave This port is the reference clock for the SysTick timer.
sysreset Signal Slave Raising this signal puts the processor into reset mode, but does not reset the debug logic.
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the processor.

ARM_SC300 - parameters

This section describes the parameters.

Table 3-131 Parameters

Name Type Default value Description
BB_PRESENT bool 0x1 Enable bitbanding.
BIGENDINIT bool 0x0 Initialize processor to big endian mode.
DBGLVL int 0x3
0
No debug.
1
Minimal debug.
2
Full debug without DWT address matching.
3
Full debug support with DWT data-comparators.
LVL_WIDTH int 0x3 Number of bits of interrupt priority.
NUM_IRQ int 0x10 Number of user interrupts.
NUM_MPU_REGION int 0x8 Number of MPU regions.
WIC bool 0x1 Include support for WIC-mode deep sleep.
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction).
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction).
master_id int 0x0 Master ID presented in bus transactions.
min_sync_level int 0x0 Force minimum syncLevel:
0
off (default)
1
syncState
2
postInsnIO
3
postInsnAll
multicycle_interruption bool 0x0 Support interruption during multicycle instructions - LDM and STM.
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting.
semihosting-cmd_line string "" Command line available to semihosting SVC calls.
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base.
semihosting-heap_limit int 0x10700000 Virtual address of top of heap.
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack.
semihosting-stack_limit int 0x10800000 Virtual address of stack limit.

ARM_SC300 - registers

This section describes the registers.

Table 3-132 Registers in Core group

Name Width Reset value Description
BASEPRI 32 0x0 BASEPRI
CONTROL 32 0x0 CONTROL
FAULTMASK 32 0x0 FAULTMASK
PRIMASK 32 0x0 PRIMASK
Rn 32 0x0 Rn, where 0 ≤ n ≤ 13.
R13_MAIN 32 0x0 MSP
R13_PROCESS 32 0x0 PSP
R14 32 0xffffffff R14
R15 32 0x0 R15
XPSR 32 0x1000000 XPSR

Table 3-133 Registers in DWT group

Name Width Reset value Description
DWT_COMPn 32 0x0 DWT Comparator Register n, where 0 ≤ n ≤ 3.
DWT_CPICNT 32 0x0 DWT CPI Counter (values are indicative and will not be the same as hardware)
DWT_CTRL 32 0x48000000 DWT Control Register
DWT_CYCCNT 32 0x0 DWT Cycle Counter (values are indicative and will not be the same as hardware)
DWT_EXCCNT 32 0x0 DWT Exception Overhead Counter (values are indicative and will not be the same as hardware)
DWT_FOLDCNT 32 0x0 DWT Instruction-Fold Counter (values are indicative and will not be the same as hardware)
DWT_FUNCTIONn 32 0x200 DWT Function Register n, where 0 ≤ n ≤ 3.
DWT_LAR 32 0x0 DWT Lock Access Register
DWT_LSR 32 0x3 DWT Lock Status Register
DWT_LSUCNT 32 0x0 DWT LSU-overhead Counter (values are indicative and will not be the same as hardware)
DWT_MASKn 32 0x0 DWT Mask Register n, where 0 ≤ n ≤ 3.
DWT_PCSR 32 0x0 DWT PC-Sample Register
DWT_SLEEPCNT 32 0x0 DWT Sleep/WFE/WFI Counter
ETMDEVAFF0 32 0x0 Device Affinity 0
ETMDEVAFF1 32 0x0 Device Affinity 1
ETMDEVARCH 32 0x0 Device Architecture
ETMTRCACATRnH 32 0x0 Address Comparator Access Type nH, where 0 ≤ n ≤ 15.
ETMTRCACATRnL 32 0x0 Address Comparator Access Type nL, where 0 ≤ n ≤ 15.
ETMTRCACVRnH 32 0x0 Address Comparator Value nH, where 0 ≤ n ≤ 15.
ETMTRCACVRnL 32 0x0 Address Comparator Value nL, where 0 ≤ n ≤ 15.
ETMTRCAUTHSTATUS 32 0x0 Authentication Status
ETMTRCAUXCTLR 32 0x0 Auxiliary Control
ETMTRCBBCTLR 32 0x0 Branch Broadcast Control
ETMTRCCCCTLR 32 0x0 Cycle Count Control
ETMTRCCIDCCTLR0 32 0x0 Context ID Comparator Control 0
ETMTRCCIDCCTLR1 32 0x0 Context ID Comparator Control 1
ETMTRCCIDCVRnH 32 0x0 ETMTRCCIDCVRnH, where 0 ≤ n ≤ 7.
ETMTRCCIDCVRnL 32 0x0 ETMTRCCIDCVRnL, where 0 ≤ n ≤ 7.
ETMTRCCIDRn 32 0x0 Component IDn, where 0 ≤ n ≤ 3.
ETMTRCCLAIMCLR 32 0x0 Claim Tag Clear
ETMTRCCLAIMSET 32 0x0 Claim Tag Set
ETMTRCCNTCTLRn 32 0x0 Counter Control n, where 0 ≤ n ≤ 2.
ETMTRCCNTRLDVRn 32 0x0 Counter Reload Value n, where 0 ≤ n ≤ 2.
ETMTRCCNTVRn 32 0x0 Counter Value Register n, where 0 ≤ n ≤ 2.
ETMTRCCONFIGR 32 0x0 Trace Configuration
ETMTRCDEVID 32 0x0 Device ID
ETMTRCDEVTYPE 32 0x0 Device Type
ETMTRCDVCMRnH 32 0x0 Data Value Comparator Mask nH, where 0 ≤ n ≤ 7.
ETMTRCDVCMRnL 32 0x0 Data Value Comparator Mask nL, where 0 ≤ n ≤ 7.
ETMTRCDVCVRnH 32 0x0 Data Value Comparator Value nH, where 0 ≤ n ≤ 7.
ETMTRCDVCVRnL 32 0x0 Data Value Comparator Value nL, where 0 ≤ n ≤ 7.
ETMTRCEVENTCTL0R 32 0x0 Event Control 0
ETMTRCEVENTCTL1R 32 0x0 Event Control 1
ETMTRCEXTINSELR 32 0x0 External Input Select
ETMTRCIDRn 32 0x0 ID n, where 0 ≤ n ≤ 13.
ETMTRCIMSPECn 32 0x0 Implementation Specific n, where 0 ≤ n ≤ 7
ETMTRCITCTRL 32 0x0 Integration Mode Control
ETMTRCLAR 32 0x0 Software Lock Access
ETMTRCLSR 32 0x0 Software Lock Status
ETMTRCOSLAR 32 0x0 OS Lock Access
ETMTRCOSLSR 32 0x0 OS Lock Status
ETMTRCPDCR 32 0x0 Powerdown Control
ETMTRCPDSR 32 0x0 Powerdown Status
ETMTRCPIDRn 32 0x0 Peripheral IDn, where 0 ≤ n ≤ 7.
ETMTRCPRGCTLR 32 0x0 Programming Control
ETMTRCPROCSELR 32 0x0 Processor Select Control
ETMTRCSEQEVRn 32 0x0 Sequencer State Transition Control n, where 0 ≤ n ≤ 2.
ETMTRCSEQRSTEVR 32 0x0 Sequencer Reset Control
ETMTRCSEQSTR 32 0x0 Sequencer State Register
ETMTRCSTALLCTLR 32 0x0 Stall Control
ETMTRCSTATR 32 0x0 Status
ETMTRCSYNCPR 32 0x0 Synchronization Period
ETMTRCTRACEIDR 32 0x0 Trace ID
ETMTRCTSCTLR 32 0x0 Global Timestamp Control
ETMTRCVDARCCTLR 32 0x0 ViewData Include/Exclude Address Range Comparator Control
ETMTRCVDCTLR 32 0x0 ViewData Main Control
ETMTRCVDSACCTLR 32 0x0 ViewData Include/Exclude Single Address Comparator Control
ETMTRCVICTLR 32 0x0 ViewInst Main Control
ETMTRCVIIECTLR 32 0x0 ViewInst Include/Exclude Control
ETMTRCVIPCSSCTLR 32 0x0 ViewInst Start/Stop Processor Comparator Control
ETMTRCVISSCTLR 32 0x0 ViewInst Start/Stop Control
ETMTRCVMIDCCTLR0 32 0x0 Virtual Machine ID Comparator Control 0
ETMTRCVMIDCCTLR1 32 0x0 Virtual Machine ID Comparator Control 1
ETMTRCVMIDCVRnH 32 0x0 ETMTRCVMIDCVRnH, where 0 ≤ n ≤ 7.
ETMTRCVMIDCVRnL 32 0x0 ETMTRCVMIDCVRnL, where 0 ≤ n ≤ 7.

Table 3-134 Registers in Debug group

Name Width Reset value Description
DCRDR 32 0x0 Debug Core Register Data Register
DCRSR 32 0x0 Debug Core Register Select Register
DEMCR 32 0x0 Debug Exception and Monitor Control Register
DFSR 32 0x0 Debug Fault Status Register
DHCSR 32 0x3010000 Debug Halting Control and Status Register

Table 3-135 Registers in FPB group

Name Width Reset value Description
FP_COMPn 32 0x0 Flash Patch Comparator Register n, where 0 ≤ n ≤ 7.
FP_CTRL 32 0x260 Flash Patch Control Register
FP_LAR 32 0x0 Flash Patch Lock Access Register
FP_LSR 32 0x0 Flash Patch Lock Status Register
FP_REMAP 32 0x20000000 Flash Patch Remap Register

Table 3-136 Registers in ID group

Name Width Reset value Description
CID0 32 0xd Component ID Register 0
CID1 32 0xe0 Component ID Register 1
CID2 32 0x5 Component ID Register 2
CID3 32 0xb1 Component ID Register 3
CPUID 32 0x410fc331 CPUID base register
ID_AFR0 32 0x0 Auxiliary Feature Register 0
ID_DFR0 32 0x100000 Debug Feature Register 0
ID_ISAR0 32 0x1101110 ISA Feature Register 0
ID_ISAR1 32 0x2111000 ISA Feature Register 1
ID_ISAR2 32 0x21112231 ISA Feature Register 2
ID_ISAR3 32 0x1111110 ISA Feature Register 3
ID_ISAR4 32 0x1310132 ISA Feature Register 4
ID_MMFR0 32 0x100030 Memory Model Feature Register 0
ID_MMFR1 32 0x0 Memory Model Feature Register 1
ID_MMFR2 32 0x1000000 Memory Model Feature Register 2
ID_MMFR3 32 0x0 Memory Model Feature Register 3
ID_PFR0 32 0x30 Processor Feature Register 0
ID_PFR1 32 0x200 Processor Feature Register 1
PID0 32 0x0 Peripheral ID Register 0
PID1 32 0xb0 Peripheral ID Register 1
PID2 32 0xb Peripheral ID Register 2
PID3 32 0x0 Peripheral ID Register 3
PID4 32 0x4 Peripheral ID Register 4
PID5 32 0x0 Peripheral ID Register 5
PID6 32 0x0 Peripheral ID Register 6
PID7 32 0x0 Peripheral ID Register 7

Table 3-137 Registers in Internal State group

Name Width Reset value Description
SEV_STATE 1 0x0 SEV/WFE event state
WAKE_WFI_NOW 1 0x0 Command to wake the core from WFI state
WFI_WAKEUP 1 0x0 WFI state
WFX_OVERRIDE 2 0x0 Override WFx behavior in ISSCompare environment

Table 3-138 Registers in MPU group

Name Width Reset value Description
MPU_CTRL 32 0x0 MPU Control Register
MPU_RASR 32 0x0 MPU Region Attribute and Size Register
MPU_RASRn 32 0x0 MPU Region Attributes and Size Register n, where 0 ≤ n ≤ 7.
MPU_RASR_An 32 0x0 MPU Region Attribute and Size Register Alias n, where 1 ≤ n ≤ 3
MPU_RBAR 32 0x0 MPU Region Base Address Register
MPU_RBARn 32 n MPU Region Base Address Register n, where 0 ≤ n ≤ 7.
MPU_RBAR_An 32 0x0 MPU Region Base Address Register Alias n, where 1 ≤ n ≤ 3
MPU_RNR 32 0x0 MPU Region Number Register
MPU_TYPE 32 0x800 MPU Type Register

Table 3-139 Registers in NVIC group

Name Width Reset value Description
NVIC_IABR0 32 0x0 NVIC IRQ Active Bit Register 0
NVIC_ICER0 32 0x0 NVIC IRQ Clear Enable Register 0
NVIC_ICPR0 32 0x0 NVIC IRQ Clear Pending Register 0
NVIC_IPRn 32 0x0 NVIC IRQ Priority Register n, where 0 ≤ n ≤ 7.
NVIC_ISER0 32 0x0 NVIC IRQ Set Enable Register 0
NVIC_ISPR0 32 0x0 NVIC IRQ Set Pending Register 0

Table 3-140 Registers in Simulation group

Name Width Reset value Description
coreRunState 32 0x0 Core run state:
0
Unknown
1
Running
2
Halted
3
Standby WFE
4
Standby WFI
5
In Reset
6
Dormant
7
Shutdown
memoryBptAccessRW 32 0x0 Last memory breakpoint hit access type:
0
none
1
read
2
write
3
rw
memoryBptAccessSize 32 0x0 Last memory breakpoint hit access size in bytes.
memoryBptAccessVA 32 0x0 Last memory breakpoint hit access virtual address.
memoryBptPC 32 0x0 Last memory breakpoint hit PC.
minSyncLevel 32 0x0 Minimum syncLevel
semihostAction 32 0x0 Semihost action:
0
unknown
1
fall through
2
intercepted
3
intercepted and stepback
syncLevel 32 0x0 Read-only: current syncLevel (0-3).
syncLevelPostInsnAllCount 32 0x0 Current number of users for SL_POST_INSN_ALL (treat as read-only).
syncLevelPostInsnAllRegister 32 0x0 Write-only: register a new user for syncLevel SL_POST_INSN_ALL.
syncLevelPostInsnAllUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_POST_INSN_ALL.
syncLevelPostInsnIOCount 32 0x0 Current number of users for SL_POST_INSN_IO (treat as read-only).
syncLevelPostInsnIORegister 32 0x0 Write-only: register a new user for syncLevel SL_POST_INSN_IO.
syncLevelPostInsnIOUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_POST_INSN_IO.
syncLevelSyncStateCount 32 0x0 Current number of users for SL_SYNC_STATE (treat as read-only).
syncLevelSyncStateRegister 32 0x0 Write-only: register a new user for syncLevel SL_SYNC_STATE.
syncLevelSyncStateUnregister 32 0x0 Write-only: unregister a new user for syncLevel SL_SYNC_STATE.

Table 3-141 Registers in Stack Limits group

Name Width Reset value Description
MSP 32 0x0 MSP
PSP 32 0x0 PSP

Table 3-142 Registers in SysTick group

Name Width Reset value Description
SYST_CALIB 32 0x0 SysTick Calibration Value Register
SYST_CSR 32 0x0 SysTick Control and Status Register
SYST_CVR 32 0x0 SysTick Current Value Register
SYST_RVR 32 0x0 SysTick Reload Value Register

Table 3-143 Registers in System Control group

Name Width Reset value Description
ACTLR 32 0x0 Auxiliary Control Register. Only bit 0 is supported for read/write. No functionality is implemented.
AFSR 32 0x0 Auxiliary Fault Status Register
AIRCR 32 0xfa050000 Application Interrupt and Reset Control Register
BFAR 32 0x0 BusFault Address Register
CCR 32 0x200 Configuration and Control Register
CFSR 32 0x0 Configurable Fault Status Registers
CPACR 32 0x0 Coprocessor Access Control Register
HFSR 32 0x0 HardFault Status Register
ICSR 32 0x0 Interrupt Control and State Register
ICTR 32 0x0 Interrupt Controller Type Register
MMFAR 32 0x0 MemManage Address Register
SCR 32 0x0 System Control Register
SFCR 32 0x0 Security Features Control Register. Read/write access is supported using SECKEY. No functionality is implemented.
SHCSR 32 0x0 System Handler Control and State Register
SHPRn 32 0x0 System Handler Priority Register n, where 1 ≤ n ≤ 3.
STIR 32 0x0 Software Trigger Interrupt Register
TRASH_REG 32 0x0 Trash Register is implemented as RAZ/WI.
VTOR 32 0x0 Vector Table Offset Register
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