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CCI550 component

This section describes the CCI550 component.

CCI550 - about

This C++ component is a model of the CCI-550 Cache Coherent Interconnect for AXI4 ACE.

CCI550 contains the following CADI targets:

  • CCI550

CCI550 contains the following MTI components:

  • CCI550
  • PVBusSlave

CCI550 - functionality

This model is compliant with the hardware except for the following limitations.

Address Decoder
  • Only supports striping down to 4KiB.
  • If the address decoder aborts the access, returns SLVERR rather than DECERR.
Interfaces
The model does not implement the Q-Channel and P-Channel interfaces.
Performance Monitoring Unit
  • PMU counters recognize only a few event sources:
    • Slave interface events:
      3ReadOnce.
      4ReadClean, ReadShared, ReadNotSharedDirty, ReadUnique.
      5MakeUnique, CleanUnique.
      6CleanInvalid, CleanShared, MakeInvalid.
      7DVM transaction received from upstream.
      9Read data that is satisfied by a snoop request.
    • No events are implemented for the global events or for the master events.
  • The PMU does not implement the event bus (EVNTBUS).
Reset signal sampling
The configuration ports acchannelensx[] are sampled in the hardware when coming out of reset. In the model, these ports are sampled at the first transaction to a pvbus_s port or to the register file.
Status Register, change-pending, and DVM messages
The Status Register provides information on when the last transaction that could have observed an old value of a snoop or DVM enable has finished in the upstream system. Therefore a port that has been disabled can now have the system upstream of that port turned off. The model does not track DVM messages in the upstream system.
Snoop filter RAMs
  • The CCI-550 hardware has a snoop filter that reduces the number of snoop requests that the interconnect has to make. The model does not have a snoop filter and could make more snoop requests than the hardware would. This difference has no programmer-visible effect.
  • The Status Register fields that relate to the power state of the Snoop filter RAMs are undefined.
Registers
The following registers provide storage but have no effect on the model.
  • QoS registers.
  • Interface monitor registers. These registers are intended for silicon debug.

CCI550 - ports

This section describes the ports.

Table 4-39 Ports

Name Protocol Type Description
acchannelensx Value Slave The acchannelensx[N] pins tell the interconnect whether the upstream system accepts snoops or DVM messages, or both.
address_decoder CCI500_AddressDecoderProtocol Master An address decoder can be attached to the address_decoder port to choose which pvbus_s port a downstream transaction goes out of. If you do not connect an address decoder, then all transactions go out of port 0.
dbgen Signal Slave Invasive debug enable.
errirq Signal Master Some async error was detected.
evntcntoverflow Signal Master The output interrupts of the event counters.
niden Signal Slave Non-invasive debug enable.
pvbus_m PVBus Master The downstream master ports.
pvbus_register_file_s PVBus Slave The slave port of the register file.
pvbus_s PVBus Slave Bus slave ports.
reset_in Signal Slave Reset the interconnect.
reset_state_of_upstream_port Signal Slave Tell the interconnect the reset state of the upstream ports. The interconnect can use the reset state to check some aspects of the reset sequencing. If you are using force_on_from_start, then you must connect these pins.
sci_s SystemCoherencyInterface Slave The System Coherency Interface bus. For upstream ports that have a corresponding bit set in the bitmap of si_system_coherency_interface, the corresponding sci_m port can be used to move the upstream system into and out of the coherency domain.
spiden Signal Slave Secure privileged invasive debug enable.
spniden Signal Slave Secure privileged non-invasive debug enable.

CCI550 - parameters

This section describes the parameters.

Table 4-40 Parameters

Name Type Allowed values Default value Description
acchannelensn uint64_t 0x0-0x3 0x0 Determine whether snoop requests are enabled or disabled from upstream port n, where 0 ≤ n ≤ 6.
addr_width uint64_t 0x20-0x30 0x28 The bit-width of the address that the CCI can accept.
cache_state_modelled bool true, false true Model the cache state.
dbgen bool true, false true Invasive debug enable. If true, enables the counting of PMU events.
force_on_from_start bool true, false false The interconnect normally starts up with snooping and DVM disabled. The parameter si_system_coherency_interface determines which connections the System Coherency Interface (SCI) manages. If the SCI manages a connection, this parameter has no effect. For all other connections, this parameter enables the upstream system of a port to be snooped if the upstream is not in reset, and if ACCHANNELENSx allows it. The interconnect does not need a software driver. Any non-SCI port that could go into reset must have reset_state_of_upstream_port[] reflect the reset state of that upstream system. Otherwise, the upstream system can receive snoop or DVM messages while in reset, which generates an error. Do not use if software is directly controlling the interconnect. This option does not disavow the responsibility of the upstream system to clean any shared dirty data from its caches before going into reset.
niden bool true, false true Whether Non-secure events are allowed to be counted in the performance monitor
num_ace_lite_ports uint64_t 0x1-0x6 0x5 The bottom num_ace_lite_ports are ACE-Lite+DVM.
num_ace_ports uint64_t 0x1-0x6 0x2 The top num_ace_ports are ACE and support full coherency.
number_of_phantom_entries uint64_t

0x1-

0xffffffff

0x20 Number of phantom entries in the cache. Phantom entries are used by certain cache operations to hold temporary data. Usually this parameter is left at the default value, which is safe for all systems containing up to 32 masters.
qos_threshold_upper uint64_t 0x0-0xf 0xc Reset value for the QoS threshold register.
reentrancy_support string - "env" Must be one of:
on
Hazard checking per cache line (normal mode)
off
No hazard checking. Use only for single master systems.
cacheglobal
Hazard checking globally for cache, not per cache line. This value is a testing feature and provokes more hazards than necessary.
env (or empty string)
Take the value from FM_REENTRANCY_SUPPORT env var. If this value is not set, use 'on'.
sin_qos_bw_regulator bool true, false false For upstream port n, where 0 ≤ n ≤ 6, determine if it has a BW regulator. The effect of QoS is not modeled and this parameter only alters some registers.
si_system_coherency_interface uint64_t 0x0-0x7f 0x0 This parameter tells the interconnect which upstream ports the System Coherency Interface controls. Each bit corresponds to an upstream port, for example bit 0 corresponds to upstream port 0. If the SCI port is connected but si_system_coherency_interface disables its use, then messages from upstream are ignored. Software must then manage the entrance to and exit from the coherency domain of the upstream system.
spiden bool true, false true Secure invasive debug enable. SPIDEN and DBGEN both being high enables the counting of both Non-secure and Secure events.
spniden bool true, false true Whether Secure and Non-secure events are allowed to be counted in the performance monitor
version string - "" The version of the interconnect. Allowed versions are r0p0 and r1p0.

CCI550 - registers

This section describes the registers.

Table 4-41 Registers in group 'Event Counter Group n', where 0 ≤ n ≤ 7

Name Width Reset value Description
Count_Control_Register_Counter_n 32 0x0 The Count Control Register controls this counter. Bit [0] is the Counter Enable Register. This register is at address 0x<n+1>0008.
Event_Count_Register_Counter_n 32 0x0 The Event Count Register Counter is the count value for the specified event. Register is at address 0x<n+1>0004.
Event_Select_Register_Counter_n 32 0x0 Choose the event the Event Select Register Counter counts. Bits [8:5] indicate the interface to monitor. Bits [4:0] indicate the event to monitor. Register is at address 0x<n+1>0000.
Overflow_Flag_Status_Register_Counter_n 32 0x0 The Overflow Flag Status Register Counter indicates when an overflow occurred. Bit [0] indicates the counter overflowed and the corresponding interrupt pin is raised. To clear the bit, write 1 to this register. Register is at address 0x<n+1>000c.

Table 4-42 Registers in group 'Global register set'

Name Width Reset value Description
Component_ID0 32 0xd Component_ID0
Component_ID1 32 0xf0 Component_ID1
Component_ID2 32 0x5 Component_ID2
Component_ID3 32 0xb1 Component_ID3
Control_Override_Register 32 0x0 Control_Override_Register
Imprecise_Error_Register 32 0x0 Imprecise_Error_Register
Interface_Monitor_Control_Register 32 0x0 Interface_Monitor_Control_Register
Performance_Monitor_Control_Register 32 0x4000 Performance_Monitor_Control_Register
Peripheral_ID0 32 0x23 Peripheral_ID0
Peripheral_ID1 32 0xb4 Peripheral_ID1
Peripheral_ID2 32 0xb Peripheral_ID2
Peripheral_ID3 32 0x0 Peripheral_ID3
Peripheral_ID4 32 0x84 Peripheral_ID4
Peripheral_ID5 32 0x0 Peripheral_ID5
Peripheral_ID6 32 0x0 Peripheral_ID6
Peripheral_ID7 32 0x0 Peripheral_ID7
QoS_Threshold_Register 32 0xc000c QoS_Threshold_Register
Secure_Access_Register 32 0x0 Secure_Access_Register
Status_Register 32 0x0 Status_Register

Table 4-43 Registers in group 'Slave Interface Group n (ACE-Lite)', where 0 ≤ n ≤ 6

Name Width Reset value Description
Max_OT_Register_SIn 32 0x0 Has no effect in the model. Register is at address 0x<n+1>110.
Read_Channel_QoS_Value_Override_Register_SIn 32 0x0 Has no effect in the model. Register is at address 0x<n+1>100.
Shareability_Override_Register_SIn 32 0x0 Controls changes to shareability on the ACE-Lite port. Register is at address 0x<n+1>004.
Snoop_Control_Register_SIn 32 0x0 Partially controls when snoops are sent to a particular slave interface. Register is at address 0x<n+1>000.
Write_Channel_QoS_Value_Override_Register_SIn 32 0x0 Has no effect in the model. Register is at address 0x<n+1>104.

CCI550 - trace sources

This section describes the trace sources.

ArchMsg.Error.reset_state_of_upstream_is_in_reset_but_trying_to_enable_snoops_andor_dvm

The upstream system is known to be in reset but an attempt is being made to enable snoops or DVM, or both, to the port. In a real system, snoop transactions could get routed to the port resulting in a deadlock, unless there were no shared transactions either in flight or already made. Fields:

is_dvm_enable bool
Is DVM enable (rather than snoop enable).
upstream_port_index unsigned int
The upstream port index of the reset signal.

ArchMsg.Error.sw_reset

An error occurred in managing the reset of upstream systems for which software manages their entrance to and exit from the coherency domain software. Fields:

why string
Why the problem occurred.

ArchMsg.Warning.acchannelensx_enables_an_upstream_port_with_no_snoop_channel

ACCHANNELENSx usually states which upstream ports have a connected snoop and DVM channels. The model has detected that an enabled port does not have a snoop or a DVM channel. This warning is ignored in the model, but might deadlock the hardware. Fields:

acchannelensx unsigned int
The value of ACCHANNELENSx that is being used.
upstream_port_index unsigned int
Upstream port index of the offending port

ArchMsg.Warning.odd_programming_trying_to_enable_upstream_port

The software tried to enable %{which} messages on port %{upstream_port_index}, which is not capable of receiving these messages. The port could be unable to receive messages because, for example, ACCHANNELENS%{upstream_port_index} disallows the receipt of the messages, or the port is entirely disconnected. Fields:

acchannelensx unsigned int
The ACCHANNELENSx bitmap of upstream ports.
bitmap_of_connected_upstream_ports unsigned int
The bitmap of upstream ports that are connected.
bitmap_of_dvm_upstream_ports unsigned int
The bitmap of DVM-capable upstream ports.
bitmap_of_full_ace_upstream_ports unsigned int
The bitmap of snoop-capable upstream ports.
upstream_port_index unsigned int
The upstream port index of the port
which enum
Which type of enable you were trying to enable

ArchMsg.Warning.reset_state_of_upstream_port_driven_after_first_transaction_seen

All signals should be driven at simulation reset so that both sides of the connection agree on the value of the wire. This trace source means that the driver of the signal did not do this. Fields:

upstream_port_index unsigned int
The upstream port index of the reset signal.
value bool
The value driven.

ArchMsg.Warning.reset_state_of_upstream_system_changed_whilst_a_snoop_change_is_pending

If the upstream system is reset while a snoop change request is pending, the system could deadlock if there is the possibility of a shared transaction in flight at the time. The upstream port might have an outstanding snoop request when it is reset and the interconnect would wait indefinitely for the response. Fields:

upstream_port_index unsigned int
The upstream port index of the reset signal.
value bool
The value driven.
why enum

Why this message is emitted.

ArchMsg.Warning.shared_transaction_received_from_upstream_port_where_acchannelensx_is_disabled

ACCHANNELENSx tells the interconnect which upstream ports do not have connected snoop channels. This warning indicates that a shared transaction was received from an upstream ACE port that ACCHANNELENSx has not enabled the snoop channel for, and there are other ports. This situation is OK if the upstream system does not accept Snoop or DVM, and so is purely an ACE-Lite system. It is also acceptable if the upstream systems are truly separate shareability domains. However, this warning might also mean that the interconnect has not been programmed, or the parameter force_on_from_start has not been used. This warning only appears once between resets of the interconnect. Fields:

upstream_port_index unsigned int
Upstream port index of the offending port

allowed_register_access

An allowed register access to the register file. Fields:

data unsigned int
The data that is read or written. If this action is a read, it is only valid if result is ok.
is_debug bool
Is the transaction a debug transaction?
is_read bool
Is the transaction a read transaction?
ns bool
The transaction is Non-secure
register enum
The register of the transaction

change_dvm_disabled_ports

Reports a bitmap of which ports are disabled to receive DVM messages. Fields:

new_bitmap unsigned int
The new bitmap of disabled ports
old_bitmap unsigned int
The old bitmap of disabled ports

change_upstream_disabled_ports

Reports a bitmap of which upstream ports of the cache are disabled so snoop requests are not sent to them. Fields:

new_bitmap unsigned int
The bitmap of upstream ports that are disabled.
old_bitmap unsigned int
The bitmap of upstream ports that are disabled.

configuration_pins

One of the configuration pins changed. In the RTL these pins are sampled at reset, but in the model they are sampled at first transaction. If sampling occurs after this point, then it is traced but the ignored field is true and the value that is reported is the intended value, not the actual value. Fields:

ignored bool
The value was ignored because it occurred after seeing a transaction.
value unsigned int
The intended value.
which enum
Which configuration pin changed.

debug_enables

The signals or parameters that cause whether events are counted or not. Fields:

dbgen bool
DBGEN value
niden bool
NIDEN value
non_secure_traceable bool
Non-secure events are traceable
secure_traceable bool
Secure events are traceable
spiden bool
SPIDEN value
spniden bool
SPNIDEN value

errirq

The error interrupt signal that is generated when there are unacknowledged imprecise errors. Fields:

value bool
The value that it is driven to.

evntcntoverflow

The event counter overflow interrupt lines. Fields:

counter_id unsigned int
The ID of the related counter.
value bool
The value of the interrupt line.

force_on_from_start

A commentary on what force_on_from_start is doing. Fields:

acchannelen_dvm unsigned int
The bitmap of which upstream ports can receive DVM messages. If the appropriate bit is clear in this register, then it is not enabled.
acchannelen_snoop unsigned int
The bitmap of which upstream ports can receive snoop messages. If the appropriate bit is clear in this register, then it is not enabled.
enable bool
Whether the upstream port is being enabled or not.
reset_state_of_upstream_system enum
What the interconnect knows about the reset state of the upstream system.
upstream_port_index unsigned int
The upstream port index.
why enum
Why the value changed.

ignored_register_access

The register access is ignored. Fields:

address enum
The address.
is_debug bool
Is the access a debug access?
is_read bool
Is the access a read access?
ns bool
The security state of the transaction.
why enum
Why the access was ignored.

imprecise_error_received

An imprecise error was received for the specified transaction. Fields:

address unsigned int
Address of the transaction.
downstream_port_index unsigned int
The downstream port index that the transaction exited from.
ns bool
Is the transaction Non-secure?

pmu_overflow

The performance monitor counter overflowed. Fields:

counter_id unsigned int
The ID of the related counter.
event_counting unsigned int
The event that the counter is counting.
new_value bool
The new value of the overflowed flag.
old_value bool
The old value of the overflowed flag.

pmu_programmed

A programmed change to the performance monitor unit counter. Fields:

counter_id unsigned int
The ID of the related counter.
current_count unsigned int
The current value of the counter.
enabled bool
Is the counter enabled?
event_counting unsigned int
The event that the counter is counting.
why enum

Why this message is emitted.

register_access

Read or write of the register file. Fields:

address unsigned int
The address of the transaction.
data unsigned int
The data that is read or written. If this action is a read, it is only valid if result is ok.
is_debug bool
Is the transaction a debug transaction?
is_read bool
Is the transaction a read transaction?
ns bool
Is the transaction Non-secure?
number_of_beats unsigned int
The number of beats in the transaction.
result enum
The result of the transaction.
width_in_bytes unsigned int
Width of the transaction in bytes.

reset_state_of_upstream_port

The interconnect uses the pins reset_state_of_upstream_port[N] to check that snoops and DVMs to upstream ports whose systems are in reset are disabled. If you connect these ports to a signal that indicates if the upstream port is in reset, then the interconnect can perform this check. This trace source is the trace of the reset state changes. Fields:

upstream_port_index unsigned int
The upstream port index of the reset signal.
value bool
The value driven.

upstream_port_with_an_unsynced_snoop_change_pending

Changing whether to send snoop requests or DVM messages to a port takes a finite time to take effect and the software should poll for completion. This trace source tells you when an upstream port has a snoop change pending on it that has not been polled for completion. Fields:

comment enum
Comment.
pending bool
Whether the change is pending or not.
upstream_port_index unsigned int
Upstream port index.
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