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MessageBox component

This section describes the MessageBox component.

MessageBox - about

This component permits passing of blocks of data, or messages, between the driver and the parent VFS2 device, with a suitable driver.

It operates as a subcomponent to the VFS2 component. It is not a hardware model, and is designed to operate efficiently within a Fast Models platform model.

This implementation is generic but primarily provides a transport layer for the VFS2 component.

A C header file, MBoxTypes.h, is supplied in the VFS2/C directory of Fast Models. This header file contains definitions of register offsets, control and status bits, and buffer sizes. The example MessageBox driver implementation in the VFS2/cpptest directory is a simple, polling implementation written in C++.

This is a LISA+ component.

MessageBox - ports

This section describes the ports.

Table 4-101 MessageBox ports

Name Protocol Type Description
pvbus_s PVBus Slave Provides memory-mapped access to the MessageBox registers and shared buffer.
message MessageBox Slave Delivers messages to the parent component, and receives messages from the parent for delivery to the target driver.
intr Signal Master Optional interrupt line used to indicate availability of incoming message data. Alternatively the status register can be polled.

MessageBox - parameters

This section describes the parameters.

Table 4-102 MessageBox parameters

Name Type Allowed values Default value Description
id Integer - 0x01400400 MessageBox ID

MessageBox - registers

This section describes the registers.

Table 4-103 MessageBox registers

Name Offset Access Description
MESSAGEBOX_ID 0x00 Read only Returns a user-configurable ID value
MESSAGEBOX_DATA 0x04 Read/write MessageBox DATA register
MESSAGEBOX_CONTROL 0x08 Read/write MessageBox CONTROL register
MESSAGEBOX_STATUS 0x0C Read only MessageBox STATUS signal bits
MESSAGEBOX_START 0x10 Read/write MessageBox START register
MESSAGEBOX_END 0x14 Read/write MessageBox END register
MESSAGEBOX_IRQMASK 0x18 Read/write Controls which of the status bits can cause the interrupt signal to be asserted

MessageBox - DATA register

Writing to the DATA register writes to the buffer at the offset specified in the END register, and increments the register by 4. Reading from the register reads from the buffer at the offset specified in the START register, and increments the register by 4.

MessageBox - CONTROL register

The CONTROL register issues commands to control message passing.

The register can have one of two values:

1
Causes the START/END registers to be reset to 0 and clears the RXREADY bit in the STATUS register. This can also be done directly by programming the START/END registers to 0.
2
Causes the buffer memory between the START/END offsets to be sent to the parent component for processing. Typically the parent component performs some processing and at some point causes an incoming packet to be constructed in the buffer and the RXREADY signal to be set.

All other values for the CONTROL register are reserved.

MessageBox - STATUS signal bits

The STATUS signal returns status bits indicating whether more data can be transferred to or from the buffer and if there is a new incoming message available.

The STATUS signal has three defined bits:

0 RXEMPTY
Set to 1 when START=END so no more receive data is available.
1 TXFULL
Set to 1 if END is incremented to the end of the buffer.
2 RXREADY
Set to 1 when an incoming packet is available for reading. This is reset to 0 when the DATA, START, or END registers are accessed.

MessageBox - START register

When using the DATA register, the START register gives the offset of the next word to read from the buffer.

When accessing the buffer directly, for outgoing messages the START register is programmed to the start of the message. For incoming messages it indicates the start of the message. The offset is relative to the buffer start.

MessageBox - END register

When using the DATA register, the END register gives the offset to the first unused word after the end of the message.

When accessing the buffer directly, for outgoing messages the END register is programmed to 1 past the end of the message. For incoming messages it indicates 1 past the end of the message. The offset is relative to the buffer start.

MessageBox - buffer

The data buffer is mapped starting at the device offset of 0x1000 and is 60KB in size, occupying the rest of the 64KB of device space. Do not use the first 4KB.

MessageBox - interrupts

The interrupt line is asserted through sg::Signal::Set whenever STATUS & IRQMASK is nonzero.

MessageBox - verification and testing

This component passes tests through use with Linux operating systems.

MessageBox - performance

ARM® expects this component to have little effect on the performance of PV systems. The component depends on the performance of the host filesystem.

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