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MMU_400 component

This section describes the MMU_400 component.

MMU_400 - about

This LISA+ component is a model of r0p1 of the ARM® CoreLink™ MMU-400 System Memory Management Unit.

MMU_400 - ports

This section describes the ports.

Table 4-107 MMU_400 ports

Name Protocol Type Description
reset_in Signal Slave Signal to reset the MMU.
pvbus_s PVBus Slave Upstream port of the MMU. Addresses on the port are in VA/IPA.
apb3_control_ns PVBus Slave APBv3 control port for Non-secure access to the register file. If this port is used do not use the APBv4 port.
apb3_control_s PVBus Slave APBv3 control port for Secure access to the register file. If this port is used do not use the APBv4 port.
apb4_control PVBus Slave APBv4 control port for access to the register file. If this port is used do not use the APBv3 ports.
cfg_cttw_in Signal Slave Enables coherent page table walks.
pvbus_m PVBus Master Downstream port of the MMU, where translated transactions emerge.
pvbs_ptw_m PVBus Master Downstream port for page table walks if configured using the ptw_has_separate_port parameter.
cfg_flt_irpt_ns Signal Master Non-secure configuration access fault interrupt. Corresponds to SMMU architectural signal SMMU_NSgCfgIrpt.
cfg_flt_irpt_s Signal Master Secure configuration access fault interrupt. Corresponds to SMMU architectural signal SMMU_gCfgIrpt.
cxt_irpt_ns Signal Master Non-secure context bank fault.
glbl_flt_irpt_ns Signal Master Global Non-secure fault interrupt. Corresponds to SMMU architectural signal SMMU_NSgIrpt.
glbl_flt_irpt_s Signal Master Global Secure fault interrupt. Corresponds to SMMU architectural signal SMMU_gIrpt.
comb_irpt_ns Signal Master Non-secure combined interrupt.
comb_irpt_s Signal Master Secure combined interrupt.

MMU_400 - parameters

This section describes the parameters.

Table 4-108 MMU_400 parameters

Name Type Allowed values Default value Description
always_secure_ssd_indices string - "" Non-programmable SSD_Indexes that are always Secure, for example 0, 6, 35-64.
cfg_cttw bool true, false true Perform coherent page table walks.
number_of_contexts int 1-8 8 Number of context banks.
number_of_smrs int 2-32 32 Number of stream match registers.
percent_tlbstatus_commits int 0-100 10 Percentage of time that a poll of TLBSTATUS commits the TLBI commands.
programmable_non_secure_by_default_ssd_indices string - "" Programmable SSD_Indexes that are Non-secure by default, for example 0, 6, 35-84.
programmable_secure_by_default_ssd_indices string - "" Programmable SSD_Indexes that are Secure by default, for example 0, 6, 35-84.
ptw_has_separate_port bool true, false true Page table walks use the pvbus_ptw_m port.
pvbus_m_is_ace_lite bool true, false true Downstream port pvbus_m is ACE-Lite.
stream_id_width int 0-15 6 StreamID bit width.
tlb_depth int 0-2048 64 TLB depth. Zero means infinite.
use_ssd_determination_table bool true, false true Use the SSD determination table.a

MMU_400 - identify() parameters

The ARM implementation of the identify() function uses these parameters to map a label of a transaction to a StreamID and either an SSD_Index or a Security State Determination (SSD).

Note

The labelN_ parameters are only used if use_label_mapping is true.

Table 4-109 MMU_400 identify() parameters

Name Type Allowed values Default value Description
use_label_mapping bool true, false true This component has two label modes. You select which one with this parameter.b
labelN_read_ssd unsigned 0-65535 0 LabelN: read SSD or SSD_Index. 0 <= N <= 31.
labelN_read_stream_id unsigned 0-65535 0 LabelN: read StreamID. 0 <= N <= 31.
labelN_write_ssd unsigned 0-65535 0 LabelN: write SSD or SSD_Index. 0 <= N <= 31.
labelN_write_stream_id unsigned 0-65535 0 LabelN: write StreamID. 0 <= N <= 31.

MMU_400 - registers

This section describes the registers.

This component models all architectural registers as the Technical Reference Manual (TRM) specifies, except for performance registers. It does not model any of the performance registers.

MMU-400 does not have an SMMU_STLBGSTATUS register because the Secure side is a nominal pass-through. MMU-400 only has stage 2 support and you cannot use stage 2 on the Secure side.

The SMMU_NSACR is an alias of the Non-secure SMMU_ACR. This component models SMMU_ACR as RAZ/WI.

The *ACR registers have IMP DEF contents. This component models only the PAGESIZE bit of the SACR, as non-RAZ/WI. It models no other IMP DEF registers.

MMU_400 - debug features

This component exports a CADI debug interface.

MMU_400 - verification and testing

This component is functionally complete and passes unit tests.

MMU_400 - performance

This component has little effect on system performance.

Just as for the hardware, TLB misses affect performance. To reduce this, increase the TLB size with the tlb_depth parameter.

a If true, the bottom 16 bits of the MasterID encode the SSD_Index. They must be < 2^ssd_index_width. If false, they encode the SSD state directly (zero is Secure and nonzero is Non-secure).
b Use true if your upstream devices have labels in the top 16 bits of the transaction MasterID. Note that the model does not have a concept of AXI-ID, but a transaction can have a MasterID set on it. Label your upstream components 0…N so that the parameters of this component can map those integers to StreamID and SSD_Index. Use false if the StreamID is encoded in the top 16 bits of the MasterID and the bottom 16 bits encode either the SSD_Index or the SSD state directly, depending on use_ssd_determination_table. Typically in hardware, a device emits different AXI-IDs, depending on what it is doing. In the model, MasterIDs are usually not diverse and a device might only emit one MasterID.
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