PL011_Uart component
This section describes the PL011_Uart component.
PL011_Uart - about
This LISA+ component is a model of r1p4 of a PL011_UART PrimeCell component.
This component does not implement the DMA functionality of the PL011 PrimeCell.
Related concepts
PL011_Uart - ports
This section describes the ports.
Table 4-114 PL011_Uart ports
Name | Protocol | Type | Description |
---|---|---|---|
pvbus |
PVBus | Slave | Slave port for connection to PV bus master/decoder |
intr |
Signal | Master | Interrupt signaling |
clk_in_ref |
ClockSignal | Slave | Clock input, typically 14.745MHz, which sets the master transmit/receive rate |
serial_out |
SerialData | Master | Used to communicate with a serial device, such as a terminal |
Related reference
PL011_Uart - parameters
This section describes the parameters.
Table 4-115 PL011_Uart parameters
Name | Type | Allowed values | Default value | Description |
---|---|---|---|---|
baud_rate |
int |
- | 38400 | Baud rate. |
clock_rate |
int |
- | 14745600,
|
Clock rate for PL011. |
in_file |
string |
- | "" | Input file for data to be read by the UART. |
in_file_escape_sequence |
string |
- | ## | Input file escape sequence. |
out_file |
string |
- | "" | Output file to hold data written by the UART. Use '-' to send all output to stdout. |
revision |
string |
- | 'r1p4' | Sets the peripheral ID register to correspond to the given revision, and also sets the FIFO capacity to 16 or 32 because this changes with the revision. |
shutdown_on_eot |
bool |
true , false |
false |
Shut down simulation on receipt of an EOT (ASCII 4) character. This is useful for regression tests when semihosting is not available. |
shutdown_tag |
string |
- | "" | Shut down simulation on receipt of this string. |
uart_enable |
bool |
true , false |
false |
Enable UART when the system starts. |
unbuffered_output |
bool |
true , false |
false |
Unbuffered output. |
untimed_fifos a |
bool |
true , false |
true |
Ignore the clock rate and allow immediate serial data transfer between the Tx/Rx FIFOs of the UART and the SerialData port. |
PL011_Uart - registers
This section describes the registers.
Table 4-116 PL011_Uart registers
Name | Offset | Access | Description |
---|---|---|---|
UARTDR |
|
Read/write | Data register |
UARTRSR |
|
Read only | Receive status register |
UARTECR |
|
Write only | Error clear register |
UARTFR |
|
Read only | Flag register |
UARTILPR |
|
Read/write | IrDA low-power counterb |
UARTIBRD |
|
Read/write | Integer baud rate divisor |
UARTFBRD |
|
Read/write | Fractional baud rate divisor |
UARTLCR_H |
|
Read/write | Line control register, high byte |
UARTCR |
|
Read/write | Control register |
UARTFLS |
|
Read/write | Interrupt FIFO level select |
UARTMSC |
|
Read/write | Interrupt mask set/clear |
UARTRIS |
|
Read only | Raw interrupt status |
UARTMIS |
|
Read only | Masked interrupt register |
UARTICR |
|
Write only | Interrupt clear register |
UARTDMACR |
|
Read/write | DMA control registerb |
PL011_Uart - verification and testing
This component passes tests as part of the VE example system by using VE test suites and by booting operating systems.
PL011_Uart - performance
ARM® expects this component to have little effect on the performance of PV systems. However, at very high baud rates such as in excess of 1MHz, simulation performance might be reduced.
When false, characters of serial data are clocked to/from the
SerialData port at a rate controlled by the clk_in_ref
clock rate and the baud-rate-divider configuration of the
UART clock. Enabling untimed_fifos
permits
serial data to be sent/received as fast as it can be generated/consumed. The
modem control signals are still generated correctly, so the UART is not able to
transmit data faster than the receiving end can handle. For example,
TelnetTerminal uses the CTS signal to avoid overflowing its TCP/IP buffer.