PL180_MCI component
This section describes the PL180_MCI component.
PL180_MCI - about
This LISA+ component is a model of the PL180 Multimedia Card Interface (MCI).
When paired with an MMC card model, the PL180_MCI component provides emulation of a flexible, persistent storage mechanism. The PL180_MMC component fully models the registers of the corresponding PrimeCell, but supports a subset of the functionality of the PL180:
- The controller supports block mode transfers, but does not currently support streaming data transfer.
- The controller can be attached to a single MMC device. The MMC bus mode and SDIO modes of the PL180 PrimeCell are not supported.
- Command and Data timeouts are not simulated.
- Payload CRC errors are not simulated.
- The DMA interface present in the PL180 PrimeCell is not modeled.
- Minimal timing is implemented within the model.
Related reference
PL180_MCI - ports
This section describes the ports.
Table 4-138 PL180_MCI ports
Name | Protocol | Type | Description |
---|---|---|---|
pvbus |
PVBus | Slave | Slave port for connection to PV bus master/decoder |
MCIINTR[ |
Signal | Master | Interrupt request ports |
mmc_m |
MMC_Protocol | Master | The MultiMediaCard (MMC) master port |
Related reference
PL180_MCI - registers
This section describes the registers.
Table 4-139 PL180_MCI registers
Name | Offset | Access | Description |
---|---|---|---|
MCIPower |
|
Read/write | Power control register |
MCIClock |
|
Read/write | Clock control register |
MCIArgument |
|
Read/write | Argument register |
MCICommand |
|
Read/write | Command register |
MCIRespCmd |
|
Read only | Response command register |
MCIResponse0 |
|
Read only | Response register |
MCIResponse1 |
|
Read only | Response register |
MCIResponse2 |
|
Read only | Response register |
MCIResponse3 |
|
Read only | Response register |
MCIDataTimer |
|
Read/write | Data timer |
MCIDataLength |
|
Read/write | Data length register |
MCIDataCtrl |
|
Read/write | Data control register |
MCIDataCnt |
|
Read only | Data counter |
MCIStatus |
|
Read only | Status register |
MCIClear |
|
write only | Clear register |
MCIMask0 |
|
Read/write | Interrupt 0 mask register |
MCIMask1 |
|
Read/write | Interrupt 1 mask register |
MCISelect |
|
Read/write | Secure Digital card select register |
MCIFifoCnt |
|
Read only | FIFO counter |
MCIFIFO |
|
Read/write | Data FIFO register |
MCIPeriphID0 |
|
Read only | Peripheral ID bits[7:0] |
MCIPeriphID1 |
|
Read only | Peripheral ID bits[15:8] |
MCIPeriphID2 |
|
Read only | Peripheral ID bits[23:16] |
MCIPeriphID3 |
|
Read only | Peripheral ID bits[31:24] |
MCIPCellID0 |
|
Read only | PrimeCell ID bits[7:0] |
MCIPCellID1 |
|
Read only | PrimeCell ID bits[15:8] |
MCIPCellID2 |
|
Read only | PrimeCell ID bits[23:16] |
MCIPCellID3 |
|
Read only | PrimeCell ID bits[31:24] |
PL180_MCI - debug features
At compile time, you can enable command tracing within the PL180_MCI component by modifying the PL180_TRACE macro in the MMC.lisa file. This sends command and event trace to standard output. You can use this output to help diagnose device driver and controller-to-card protocol issues.
PL180_MCI - verification and testing
This component passes tests in conjunction with the ARM MMC reference model, and in the VE example with Boot Monitor and Linux drivers.