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PL390_GIC component

This section describes the PL390, which is a Generic Interrupt Controller (GIC).

PL390_GIC - about

This LISA and C++ component is a model of r0p0 of the ARM® PrimeCell Generic Interrupt Controller (PL390), which implements the Generic Interrupt Controller Architecture Specification.

The GIC provides support for three interrupt types:

  • Software Generated Interrupt (SGI).
  • Private Peripheral Interrupt (PPI).
  • Shared Peripheral Interrupt (SPI).

You can set:

  • Security state for an interrupt.
  • Priority state for an interrupt.
  • Enabling or disabling state for an interrupt.
  • Processors that receive an interrupt.

PL390_GIC - ports

This section describes the ports.

Table 4-159 PL390_GIC ports

Name Protocol Type Description
nfiq[8] Signal Master Send out FIQ signal to processor <n>
nirq[8] Signal Master Send out IRQ signal to processor <n>
ppi_c0[16] Signal Slave Private peripheral interrupt for processor 0 (num_cpus> = 1)
ppi_c1[16] Signal Slave Private peripheral interrupt for processor 1 (num_cpus> = 2)
ppi_c2[16] Signal Slave Private peripheral interrupt for processor 2 (num_cpus> = 3)
ppi_c3[16] Signal Slave Private peripheral interrupt for processor 3 (num_cpus> = 4)
ppi_c4[16] Signal Slave Private peripheral interrupt for processor 4 (num_cpus> = 5)
ppi_c5[16] Signal Slave Private peripheral interrupt for processor 5 (num_cpus> = 6)
ppi_c6[16] Signal Slave Private peripheral interrupt for processor 6 (num_cpus> = 7)
ppi_c7[16] Signal Slave Private peripheral interrupt for processor 7 (num_cpus> = 8)
pvbus_cpu PVBus Slave Slave port for connection to processor interface
pvbus_distributor PVBus Slave Slave port for connection to distributor interface
enable_c[8] Value Slave Compared with masked PVBus master id to select processor interface: (master_id & enable_c<n>) == match_c<n>
match_c[8] Value Slave Mask on the PVBus master id to select processor interface: (master_id & enable_c<n>) == match_c<n>
enable_d[8] Value Slave Compared with masked PVBus master id to select distributor interface: (master_id & enable_d<n>) == match_d<n>
match_d[8] Value Slave Mask on the PVBus master id to select distributor interface: (master_id & enable_d<n>) == match_d<n>
legacy_nfiq[8] Signal Slave Legacy FIQ interrupt for processor Interface <n>
legacy_nirq[8] Signal Slave Legacy IRQ interrupt for processor Interface <n>
cfgsdisable Signal Slave Set preventing write accesses to security-critical configuration registers
reset_in Signal Slave Reset signal
spi[988] Signal Slave Shared peripheral interrupt inputs

PL390_GIC - parameters

This section describes the parameters.

Table 4-160 PL390_GIC parameters

Name Type Allowed values Default value Description
ARCHITECTURE_VERSION Integer 0-1 1 Set architecture version in periph_id register
AXI_IF Boolean true, false true  
C_ID_WIDTH Integer 0-32 32 Width of the processor interface master id
D_ID_WIDTH Integer 0-32 32 Width of the distributor interface master id
ENABLE_LEGACY_FIQ Boolean true, false true Provide legacy fiq interrupt inputs
ENABLE_LEGACY_FIQ Boolean true, false true Provide legacy irq interrupt inputs
ENABLE_PPI_EDGE Boolean true, false false PPI edge sensitive
ENABLE_TRUSTZONE Boolean true, false true Support trust zone
INIT_ENABLE_C0 to INIT_ENABLE_C7 Integer - 0xFFFFFFFF INIT value of ENABLE_C<n>
INIT_ENABLE_D0 to INIT_ENABLE_D7 Integer - 0xFFFFFFFF INIT value of ENABLE_D<n>
INIT_MATCH_C0 to INIT_MATCH_C7 Integer - 0xFFFFFFFF INIT value of MATCH_C<n>
INIT_MATCH_D0 to INIT_MATCH_D7 Integer - 0xFFFFFFFF INIT value of MATCH_D<n>
NUM_CPU Integer 1-8 8 Number of processor interfaces
NUM_LSPI Integer 0-31 31 Number of lockable SPIs
NUM_PPI Integer 0-16 16 Number of private peripheral interrupts
NUM_PRIORITY_LEVELS Integer 16, 32, 64, 128, 256 256 Number of priority levels
NUM_SGI Integer 0-16 16 Number of software generated interrupts
NUM_SPI Integer 0-988 988 Number of shared peripheral interrupts

PL390_GIC - registers

This section describes the registers.

A processor interface consists of a pair of interfaces, pvbus_cpu and pvbus_distributor. The enable_c<n> and match_c<n> signals identify the originator of a transaction on pvbus_cpu. Similarly, enable_d<n> and match_d<n> signals identify the originator of a transaction on pvbus_distributor. <n> corresponds to the number of a processor interface.

To reduce compile time, the registers are not available by default. To activate them, uncomment one of the following statements in PL390_GIC.lisa:

// #define FEW_CADI_REGISTER
// #define ALL_CADI_REGISTER

Table 4-161 PL 390_GIC registers: distributor interface

Name Offset Access Description
enable 0xD0000 Read/write ICDICR [S]: Interrupt Control Register
enable_ns 0xD0001 Read/write ICDICR [NS]: Interrupt Control Register
ic_type 0xD0008 Read only ICDDIIR: Distributor Implementer Identification Register
sgi_security_if<n> 0xDn080 Read/write ICDISR: SGI Interrupt Security Register Interrupt ID 0-15
ppi_security_if<n> 0xDn080 Read/write ICDISR: PPI Interrupt Security Register Interrupt ID 16-31
spi_security_0-31 0xD0084 Read/write ICDISR: SPI Interrupt Security Register Interrupt ID 32-63
spi_security_32-63 0xD0088 Read/write ICDISR: SPI Interrupt Security Register Interrupt ID 64-95
...      
spi_security_960-987 0xD00FC Read/write ICDISR: SPI Interrupt Security Register Interrupt ID 992-1019
sgi_enable_set_if<n> 0xDn100 Read only ICDISER: SGI Enable Set Register Interrupt ID 0-15
ppi_enable_set_if<n> 0xDn100 Read only ICDISER: PPI Enable Set Register Interrupt ID 16-31
spi_enable_set_0-31 0xD0104 Read only ICDISER: SPI Enable Set Register Interrupt ID 32-63
spi_enable_set_32-63 0xD0108 Read only ICDISER: SPI Enable Set Register Interrupt ID 64-95
...      
spi_enable_set_960-987 0xD017C Read only ICDISER: SPI Enable Set Register Interrupt ID 922-1019
sgi_enable_clear_if<n> 0xDn180 Read only ICDICER: SGI Enable Clear Register Interrupt ID 0-15
ppi_enable_clear_if<n> 0xDn182 Read only ICDICER: SGI Enable Clear Register Interrupt ID 16-31
spi_enable_clear_0-31 0xDn182 Read only ICDICER: SGI Enable Clear Register Interrupt ID 32-63
spi_enable_clear_32-63 0xD0188 Read only ICDICER: SGI Enable Clear Register Interrupt ID 32-63
...      
spi_enable_clear_960-987 0xD01FC Read only ICDICER: SGI Enable Clear Register Interrupt ID 32-63
sgi_pending_set_if<n> 0xDn200 Read only ICDISPR: SGI Pending Set Register Interrupt ID 0-15
ppi_pending_set_if<n> 0xDn202 Read only ICDISPR: PPI Pending Set Register Interrupt ID 16-31
spi_pending_set_0-31 0xD0204 Read only ICDISPR: SPI Pending Set Register Interrupt ID 32-63
spi_pending_set_32-63 0xD0208 Read only ICDISPR: SPI Pending Set Register Interrupt ID 64-95
...      
spi_pending_set_960-987 0xD027C Read only ICDISPR: SPI Pending Set Register Interrupt ID 992-1019
sgi_pending_clear_if<n> 0xDn280 Read only ICDICPR: SGI Pending Clear Register Interrupt ID 0-15
ppi_pending_clear_if<n> 0xDn282 Read only ICDICPR: SGI Pending Clear Register Interrupt ID 16-31
spi_pending_clear_0-31 0xDn284 Read only ICDICPR: SGI Pending Clear Register Interrupt ID 32-63
spi_pending_clear_32-63 0xD0288 Read only ICDICPR: SGI Pending Clear Register Interrupt ID 64-95
...      
spi_pending_clear_960- 987 0xD037C Read only ICDICPR: SGI Pending Clear Register Interrupt ID 992-1019
priority_sgi_if<n>_0-3 0xDn400 Read/write ICDIPR: SGI Priority Level Register Interrupt ID 0-3
...      
priority_sgi_if<n>_12-15 0xDn40C Read/write ICDIPR: SGI Priority Level Register Interrupt ID 12-15
priority_ppi_if<n>_0-3 0xDn410 Read/write ICDIPR: PPI Priority Level Register Interrupt ID 16-19
...      
priority_ppi_if<n>_12-15 0xDn41C Read/write ICDIPR: PPI Priority Level Register Interrupt ID 28-31
priority_spi_0-3 0xD0420 Read/write ICDIPR: PPI Priority Level Register Interrupt ID 28-31
...      
priority_spi_984-987 0xD07F8 Read/write ICDIPR: PPI Priority Level Register Interrupt ID 28-31
target_sgi_i<n>0_0-3 0xDn800 Read only ICDIPTR: SGI Target Register Interrupt ID 0-3
...      
target_sgi_i<n>0_12-15 0xDn80C Read only ICDIPTR: SGI Target Register Interrupt ID 12-15
target_ppi_i<n>0_0-3 0xDn810 Read only ICDIPTR: PPI Target Register Interrupt ID 16-19
...      
target_ppi_i<n>0_12-15 0xDn81C Read only ICDIPTR: PPI Target Register Interrupt ID 28-31
target_spi_0-3 0xD0820 Read/write ICDIPTR: SPI Target Register Interrupt ID 32-35
...      
target_spi_984-987 0xD0BF8 Read/write ICDIPTR: SPI Target Register Interrupt ID 32-35
sgi_config_if<n>_0-15 0xDnC00 Read only ICDICR: SGI Interrupt Configuration Register Interrupt ID 0-15
ppi_config_if<n>_0-15 0xDnC04 Read only ICDICR: SGI Interrupt Configuration Register Interrupt ID 0-15
spi_config_0-15 0xD0C08 Read/write ICDICR: SPI Interrupt Configuration Register Interrupt ID 32-47
...      
spi_config_976-987 0xD0CFC Read/write ICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019
ppi_if<n> 0xDnD00 Read only ICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019
spi_0-31 0xD0D04 Read only ICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019
...      
spi_960-987 0xD0D7C Read only SPI Status Register Interrupt ID 992-1019
legacy_int<n> 0xDnDD0 Read only Legacy Interrupt Register
match_d<n> 0xDnDE0 Read only Match Register
enable_d<n> 0xDnDE4 Read only Enable Register
sgi_control 0xD0F00 Read/write ICDSGIR: Software Generated Interrupt Register
periph_id_d_8 0xD0FC0 Read only Peripheral Identification Register 8
periph_id_d_4-7 0xD0FD0 Read only Peripheral Identification Register [7:4]
periph_id_d_0-3 0xD0FE0 Read only Peripheral Identification Register [7:4]
component_id 0xD0FF0 Read only PrimeCell Identification Register

PL390_GIC - debug features

This component provides some registers for functional verification and integration testing.

PL390_GIC - verification and testing

This component has been run against the RTL validation suite and has been successfully used in validation platforms.

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